phy/s7ddrphy/usddrphy: Use explicit sys clock domain on ClockSignal/ResetSignal.
Improve readability.
This commit is contained in:
Florent Kermarrec
parent
5cd192a708
commit
04334ae141
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@ -129,9 +129,9 @@ class S7DDRPHY(Module, AutoCSR):
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p_TRISTATE_WIDTH = 1,
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p_DATA_RATE_OQ = "DDR",
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p_DATA_RATE_TQ = "BUF",
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i_RST = ResetSignal() | self._rst.storage,
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i_RST = ResetSignal("sys") | self._rst.storage,
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i_CLK = ClockSignal(ddr_clk),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{n+1}": (0b10101010 >> n) & 0b1 for n in range(8)},
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o_OQ = sd_clk_se_nodelay,
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i_OCE = 1,
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@ -146,7 +146,7 @@ class S7DDRPHY(Module, AutoCSR):
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_ODELAY_TYPE = "VARIABLE",
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p_ODELAY_VALUE = 0,
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i_C = ClockSignal(),
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i_C = ClockSignal("sys"),
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i_LD = self._cdly_rst.re | self._rst.storage,
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i_LDPIPEEN = 0,
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i_CE = self._cdly_inc.re,
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@ -187,9 +187,9 @@ class S7DDRPHY(Module, AutoCSR):
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p_TRISTATE_WIDTH = 1,
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p_DATA_RATE_OQ = "DDR",
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p_DATA_RATE_TQ = "BUF",
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i_RST = ResetSignal() | self._rst.storage,
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i_RST = ResetSignal("sys") | self._rst.storage,
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i_CLK = ClockSignal(ddr_clk),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{n+1}": getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)},
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i_OCE = 1,
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o_OQ = oq if with_odelay else pad[i],
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@ -204,7 +204,7 @@ class S7DDRPHY(Module, AutoCSR):
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_ODELAY_TYPE = "VARIABLE",
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p_ODELAY_VALUE = 0,
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i_C = ClockSignal(),
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i_C = ClockSignal("sys"),
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i_LD = self._cdly_rst.re | self._rst.storage,
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i_LDPIPEEN = 0,
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i_CE = self._cdly_inc.re,
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@ -242,9 +242,9 @@ class S7DDRPHY(Module, AutoCSR):
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p_TRISTATE_WIDTH = 1,
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p_DATA_RATE_OQ = "DDR",
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p_DATA_RATE_TQ = "BUF",
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i_RST = ResetSignal() | self._rst.storage,
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i_RST = ResetSignal("sys") | self._rst.storage,
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i_CLK = ClockSignal(ddr_clk) if with_odelay else ClockSignal(ddr_clk+"_dqs"),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{n+1}": dqs_bitslip.o[n] for n in range(8)},
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i_OCE = 1,
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o_OFB = dqs_o_no_delay if with_odelay else Signal(),
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@ -263,7 +263,7 @@ class S7DDRPHY(Module, AutoCSR):
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p_PIPE_SEL = "FALSE",
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p_ODELAY_TYPE = "VARIABLE",
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p_ODELAY_VALUE = half_sys8x_taps,
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i_C = ClockSignal(),
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i_C = ClockSignal("sys"),
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i_LD = (self._dly_sel.storage[i] & self._wdly_dqs_rst.re) | self._rst.storage,
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i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
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i_LDPIPEEN = 0,
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@ -294,9 +294,9 @@ class S7DDRPHY(Module, AutoCSR):
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p_TRISTATE_WIDTH = 1,
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p_DATA_RATE_OQ = "DDR",
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p_DATA_RATE_TQ = "BUF",
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i_RST = ResetSignal() | self._rst.storage,
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i_RST = ResetSignal("sys") | self._rst.storage,
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i_CLK = ClockSignal(ddr_clk),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{n+1}": dm_o_bitslip.o[n] for n in range(8)},
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i_OCE = 1,
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o_OQ = dm_o_nodelay if with_odelay else pads.dm[i],
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@ -311,7 +311,7 @@ class S7DDRPHY(Module, AutoCSR):
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_ODELAY_TYPE = "VARIABLE",
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p_ODELAY_VALUE = 0,
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i_C = ClockSignal(),
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i_C = ClockSignal("sys"),
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i_LD = (self._dly_sel.storage[i] & self._wdly_dq_rst.re) | self._rst.storage,
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i_LDPIPEEN = 0,
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i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re,
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@ -344,9 +344,9 @@ class S7DDRPHY(Module, AutoCSR):
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p_TRISTATE_WIDTH = 1,
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p_DATA_RATE_OQ = "DDR",
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p_DATA_RATE_TQ = "BUF",
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i_RST = ResetSignal() | self._rst.storage,
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i_RST = ResetSignal("sys") | self._rst.storage,
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i_CLK = ClockSignal(ddr_clk),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{n+1}": dq_o_bitslip.o[n] for n in range(8)},
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i_TCE = 1,
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i_T1 = ~dq_oe_delay.output,
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@ -366,10 +366,10 @@ class S7DDRPHY(Module, AutoCSR):
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p_DATA_RATE = "DDR",
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p_NUM_CE = 1,
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p_IOBDELAY = "IFD",
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i_RST = ResetSignal() | self._rst.storage,
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i_RST = ResetSignal("sys") | self._rst.storage,
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i_CLK = ClockSignal(ddr_clk),
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i_CLKB = ~ClockSignal(ddr_clk),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_BITSLIP = 0,
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i_CE1 = 1,
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i_DDLY = dq_i_delayed,
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@ -387,7 +387,7 @@ class S7DDRPHY(Module, AutoCSR):
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p_PIPE_SEL = "FALSE",
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p_ODELAY_TYPE = "VARIABLE",
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p_ODELAY_VALUE = 0,
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i_C = ClockSignal(),
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i_C = ClockSignal("sys"),
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i_LD = (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re)| self._rst.storage,
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i_LDPIPEEN = 0,
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i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
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@ -404,7 +404,7 @@ class S7DDRPHY(Module, AutoCSR):
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p_PIPE_SEL = "FALSE",
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p_IDELAY_TYPE = "VARIABLE",
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p_IDELAY_VALUE = 0,
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i_C = ClockSignal(),
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i_C = ClockSignal("sys"),
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i_LD = (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | self._rst.storage,
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i_LDPIPEEN = 0,
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i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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@ -144,7 +144,7 @@ class USDDRPHY(Module, AutoCSR):
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal("ic") | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_D = 0b10101010,
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o_OQ = clk_o_nodelay,
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),
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@ -157,7 +157,7 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
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i_CLK = ClockSignal(),
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i_CLK = ClockSignal("sys"),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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@ -205,7 +205,7 @@ class USDDRPHY(Module, AutoCSR):
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal("ic") | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_D = Cat(*[getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)]),
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o_OQ = o_nodelay,
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),
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@ -218,7 +218,7 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
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i_CLK = ClockSignal(),
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i_CLK = ClockSignal("sys"),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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@ -271,7 +271,7 @@ class USDDRPHY(Module, AutoCSR):
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal("ic") | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_T = ~dqs_oe_delay.output,
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i_D = dqs_bitslip.o,
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o_OQ = dqs_nodelay,
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@ -289,7 +289,7 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_VALUE = int(tck*1e12/4),
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o_CNTVALUEOUT = self._half_sys8x_taps.status if (i == 0) and (j == 0) else Signal(),
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i_RST = ResetSignal("ic"),
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i_CLK = ClockSignal(),
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i_CLK = ClockSignal("sys"),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
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i_INC = 1,
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@ -330,7 +330,7 @@ class USDDRPHY(Module, AutoCSR):
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal("ic") | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_D = dm_o_bitslip.o,
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o_OQ = dm_o_nodelay,
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),
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@ -346,7 +346,7 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_VALUE = 0,
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i_RST = ResetSignal("ic") | (self._dly_sel.storage[i] & self._wdly_dq_rst.re) | self._rst.storage,
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i_EN_VTC = self._en_vtc.storage,
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i_CLK = ClockSignal(),
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i_CLK = ClockSignal("sys"),
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i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re,
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i_INC = 1,
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i_ODATAIN = dm_o_nodelay,
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@ -380,7 +380,7 @@ class USDDRPHY(Module, AutoCSR):
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal("ic") | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_D = dq_o_bitslip.o,
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i_T = ~dq_oe_delay.output,
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o_OQ = dq_o_nodelay,
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@ -399,7 +399,7 @@ class USDDRPHY(Module, AutoCSR):
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i_RST = ResetSignal("ic") | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLK_B = ClockSignal("sys4x"), # locally inverted
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i_CLKDIV = ClockSignal(),
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i_CLKDIV = ClockSignal("sys"),
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i_D = dq_i_delayed,
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i_FIFO_RD_EN = 0,
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o_Q = dq_i_bitslip.i,
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@ -417,7 +417,7 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = ResetSignal("ic") | (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re) | self._rst.storage,
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i_CLK = ClockSignal(),
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i_CLK = ClockSignal("sys"),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
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i_INC = 1,
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@ -436,7 +436,7 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = ResetSignal("ic") | (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | self._rst.storage,
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i_CLK = ClockSignal(),
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i_CLK = ClockSignal("sys"),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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i_INC = 1,
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