Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/ecp5ddrphy: simplify using new get_sys_phase.

This commit is contained in:
Florent Kermarrec 2020-09-30 19:39:10 +02:00
parent 207b8f48bb
commit 05ed5bf59d
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
litedram/phy/ecp5ddrphy.py
View File

@ -122,8 +122,8 @@ class ECP5DDRPHY(Module, AutoCSR):
self.datavalid = Signal(databits//8) self.datavalid = Signal(databits//8)
# PHY settings ----------------------------------------------------------------------------- # PHY settings -----------------------------------------------------------------------------
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
self.settings = PhySettings( self.settings = PhySettings(
phytype = "ECP5DDRPHY", phytype = "ECP5DDRPHY",
memtype = memtype, memtype = memtype,
@ -133,11 +133,11 @@ class ECP5DDRPHY(Module, AutoCSR):
nphases = nphases, nphases = nphases,
rdphase = rdphase, rdphase = rdphase,
wrphase = wrphase, wrphase = wrphase,
rdcmdphase = rdcmdphase, rdcmdphase = (rdphase - 1)%nphases,
wrcmdphase = wrcmdphase, wrcmdphase = (wrphase - 1)%nphases,
cl = cl, cl = cl,
cwl = cwl, cwl = cwl,
read_latency = 2 + cl_sys_latency + 2 + log2_int(4//nphases) + 5, read_latency = cl_sys_latency + 10,
write_latency = cwl_sys_latency write_latency = cwl_sys_latency
) )