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litedram_gen: Add ECLKBRIDGECS for ECP5 clock 

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
This commit is contained in:
Matt Johnston 2021-08-20 11:24:49 +08:00
parent 367231322d
commit 06ca898c69
1 changed files with 6 additions and 1 deletions
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7
litedram/gen.py
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@ -317,14 +317,19 @@ class LiteDRAMECP5DDRPHYCRG(Module):
self.sync.por += If(~por_done, por_count.eq(por_count - 1)) self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL. # PLL.
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | rst | self.rst) self.comb += pll.reset.eq(~por_done | rst | self.rst)
pll.register_clkin(clk, core_config["input_clk_freq"]) pll.register_clkin(clk, core_config["input_clk_freq"])
pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"]) pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"])
pll.create_clkout(self.cd_init, core_config["init_clk_freq"]) pll.create_clkout(self.cd_init, core_config["init_clk_freq"])
self.specials += [ self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
i_SEL = 0,
o_ECSOUT = sys2x_clk_ecsout),
Instance("ECLKSYNCB", Instance("ECLKSYNCB",
i_ECLKI = self.cd_sys2x_i.clk, i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop, i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk), o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF", Instance("CLKDIVF",