Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/s7ddrphy: increase write_latency by 1 (now possible with previous BitSlip chantges).

This commit is contained in:
Florent Kermarrec 2020-10-08 18:08:36 +02:00
parent 3fddff3a11
commit 0ac23fde52
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litedram/phy/s7ddrphy.py
View File

@ -98,7 +98,7 @@ class S7DDRPHY(Module, AutoCSR):
cl = cl, cl = cl,
cwl = cwl, cwl = cwl,
read_latency = cl_sys_latency + 6, read_latency = cl_sys_latency + 6,
write_latency = cwl_sys_latency - 2, write_latency = cwl_sys_latency - 1,
cmd_latency = cmd_latency, cmd_latency = cmd_latency,
cmd_delay = cmd_delay, cmd_delay = cmd_delay,
) )