phy/s7ddrphy: increase write_latency by 1 (now possible with previous BitSlip chantges).

2020-10-08 18:08:36 +02:00 · 2020-10-08 18:08:36 +02:00 · 0ac23fde52
parent 3fddff3a11
commit 0ac23fde52
1 changed files with 1 additions and 1 deletions
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@ -98,7 +98,7 @@ class S7DDRPHY(Module, AutoCSR):
            cl            = cl,
            cwl           = cwl,
            read_latency  = cl_sys_latency + 6,
-            write_latency = cwl_sys_latency - 2,
+            write_latency = cwl_sys_latency - 1,
            cmd_latency   = cmd_latency,
            cmd_delay     = cmd_delay,
        )