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improve ddr3 electrical settings

This commit is contained in:
Florent Kermarrec 2018-08-21 10:45:42 +02:00
parent 697eaafc4c
commit 0b6e21ab6d
2 changed files with 46 additions and 25 deletions
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13
litedram/common.py
View File

@ -10,8 +10,7 @@ class PhySettings:
nphases, nphases,
rdphase, wrphase, rdphase, wrphase,
rdcmdphase, wrcmdphase, rdcmdphase, wrcmdphase,
cl, read_latency, write_latency, cwl=0, cl, read_latency, write_latency, cwl=None):
rtt_nom='40ohm', drive_strength='40ohm', dynamic_odt='60ohm'):
self.memtype = memtype self.memtype = memtype
self.dfi_databits = dfi_databits self.dfi_databits = dfi_databits
@ -26,10 +25,12 @@ class PhySettings:
self.write_latency = write_latency self.write_latency = write_latency
self.cwl = cwl self.cwl = cwl
# board tuning parameters # Optional DDR3 electrical settings
self.rtt_nom = rtt_nom def add_electrical_settings(rtt_nom, rtt_wr, ron):
self.drive_strength = drive_strength assert self.memtype == "DDR3"
self.dynamic_odt = dynamic_odt self.rtt_nom = rtt_nom # Non-Writes on-die termination impedance
self.rtt_wr = rtt_wr # Writes on-die termination impedance
self.ron = ron # Output driver impedance
class GeomSettings: class GeomSettings:

58
litedram/sdram_init.py
View File

@ -175,9 +175,9 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
mr0 |= wr_to_mr0[wr] << 9 mr0 |= wr_to_mr0[wr] << 9
return mr0 return mr0
def format_mr1(output_drive_strength, rtt_nom): def format_mr1(ron, rtt_nom):
mr1 = ((output_drive_strength >> 0) & 1) << 1 mr1 = ((ron >> 0) & 1) << 1
mr1 |= ((output_drive_strength >> 1) & 1) << 5 mr1 |= ((ron >> 1) & 1) << 5
mr1 |= ((rtt_nom >> 0) & 1) << 2 mr1 |= ((rtt_nom >> 0) & 1) << 2
mr1 |= ((rtt_nom >> 1) & 1) << 6 mr1 |= ((rtt_nom >> 1) & 1) << 6
mr1 |= ((rtt_nom >> 2) & 1) << 9 mr1 |= ((rtt_nom >> 2) & 1) << 9
@ -188,26 +188,46 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
mr2 |= rtt_wr << 9 mr2 |= rtt_wr << 9
return mr2 return mr2
z_to_rttnom = { z_to_rtt_nom = {
'disabled' : 0, "disabled" : 0,
'60ohm' : 1, "60ohm" : 1,
'120ohm' : 2, "120ohm" : 2,
'40ohm' : 3, "40ohm" : 3,
'20ohm' : 4, "20ohm" : 4,
'30ohm' : 5 "30ohm" : 5
} }
z_to_output_drive_strength = {
'40ohm' : 0, z_to_rtt_wr = {
'34ohm' : 1, "disabled" : 0,
"60ohm" : 1,
"120ohm" : 2,
} }
z_to_dynamic_odt = {
'disabled' : 0, z_to_ron = {
'60ohm' : 1, "40ohm" : 0,
'120ohm' : 2, "34ohm" : 1,
} }
# default electrical settings (point to point)
rtt_nom = "60ohm"
rtt_wr = "120ohm"
ron = "34ohm"
# override electrical settings if specified
if hasattr(sdram_phy_settings, "rtt_nom"):
rtt_nom = sdram_phy_settings.rtt_nom
if hasattr(sdram_phy_settings, "rtt_wr"):
rtt_wr = sdram_phy_settings.rtt_wr
if hasattr(sdram_phy_settings, "ron"):
ron = sdram_phy_settings.ron
mr0 = format_mr0(bl, cl, 14, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK) mr0 = format_mr0(bl, cl, 14, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
mr1 = format_mr1(z_to_output_drive_strength[sdram_phy_settings.drive_strength], z_to_rttnom[sdram_phy_settings.rtt_nom]) mr1 = format_mr1(
mr2 = format_mr2(sdram_phy_settings.cwl, z_to_dynamic_odt[sdram_phy_settings.dynamic_odt]) z_to_ron[ron],
z_to_rtt_nom[rtt_nom])
mr2 = format_mr2(
sdram_phy_settings.cwl,
z_to_rtt_wr[rtt_wr])
mr3 = 0 mr3 = 0
init_sequence = [ init_sequence = [