improve ddr3 electrical settings
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@ -10,8 +10,7 @@ class PhySettings:
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nphases,
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rdphase, wrphase,
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rdcmdphase, wrcmdphase,
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cl, read_latency, write_latency, cwl=0,
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rtt_nom='40ohm', drive_strength='40ohm', dynamic_odt='60ohm'):
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cl, read_latency, write_latency, cwl=None):
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self.memtype = memtype
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self.dfi_databits = dfi_databits
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@ -26,10 +25,12 @@ class PhySettings:
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self.write_latency = write_latency
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self.cwl = cwl
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# board tuning parameters
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self.rtt_nom = rtt_nom
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self.drive_strength = drive_strength
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self.dynamic_odt = dynamic_odt
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# Optional DDR3 electrical settings
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def add_electrical_settings(rtt_nom, rtt_wr, ron):
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assert self.memtype == "DDR3"
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self.rtt_nom = rtt_nom # Non-Writes on-die termination impedance
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self.rtt_wr = rtt_wr # Writes on-die termination impedance
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self.ron = ron # Output driver impedance
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class GeomSettings:
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@ -175,9 +175,9 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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mr0 |= wr_to_mr0[wr] << 9
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return mr0
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def format_mr1(output_drive_strength, rtt_nom):
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mr1 = ((output_drive_strength >> 0) & 1) << 1
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mr1 |= ((output_drive_strength >> 1) & 1) << 5
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def format_mr1(ron, rtt_nom):
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mr1 = ((ron >> 0) & 1) << 1
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mr1 |= ((ron >> 1) & 1) << 5
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mr1 |= ((rtt_nom >> 0) & 1) << 2
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mr1 |= ((rtt_nom >> 1) & 1) << 6
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mr1 |= ((rtt_nom >> 2) & 1) << 9
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@ -188,26 +188,46 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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mr2 |= rtt_wr << 9
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return mr2
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z_to_rttnom = {
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'disabled' : 0,
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'60ohm' : 1,
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'120ohm' : 2,
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'40ohm' : 3,
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'20ohm' : 4,
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'30ohm' : 5
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z_to_rtt_nom = {
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"disabled" : 0,
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"60ohm" : 1,
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"120ohm" : 2,
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"40ohm" : 3,
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"20ohm" : 4,
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"30ohm" : 5
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}
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z_to_output_drive_strength = {
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'40ohm' : 0,
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'34ohm' : 1,
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z_to_rtt_wr = {
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"disabled" : 0,
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"60ohm" : 1,
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"120ohm" : 2,
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}
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z_to_dynamic_odt = {
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'disabled' : 0,
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'60ohm' : 1,
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'120ohm' : 2,
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z_to_ron = {
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"40ohm" : 0,
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"34ohm" : 1,
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}
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# default electrical settings (point to point)
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rtt_nom = "60ohm"
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rtt_wr = "120ohm"
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ron = "34ohm"
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# override electrical settings if specified
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if hasattr(sdram_phy_settings, "rtt_nom"):
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rtt_nom = sdram_phy_settings.rtt_nom
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if hasattr(sdram_phy_settings, "rtt_wr"):
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rtt_wr = sdram_phy_settings.rtt_wr
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if hasattr(sdram_phy_settings, "ron"):
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ron = sdram_phy_settings.ron
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mr0 = format_mr0(bl, cl, 14, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
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mr1 = format_mr1(z_to_output_drive_strength[sdram_phy_settings.drive_strength], z_to_rttnom[sdram_phy_settings.rtt_nom])
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mr2 = format_mr2(sdram_phy_settings.cwl, z_to_dynamic_odt[sdram_phy_settings.dynamic_odt])
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mr1 = format_mr1(
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z_to_ron[ron],
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z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(
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sdram_phy_settings.cwl,
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z_to_rtt_wr[rtt_wr])
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mr3 = 0
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init_sequence = [
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