litedram_gen: Set default csr_data_width to 32 (similar to LiteX).

2021-10-07 15:05:56 +02:00 · 2021-10-07 15:05:56 +02:00 · 0bb3bff8af
parent 6b0a35b309
commit 0bb3bff8af
1 changed files with 1 additions and 1 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -477,7 +477,7 @@ class LiteDRAMCore(SoCCore):
        sys_clk_freq   = core_config["sys_clk_freq"]
        cpu_type       = core_config["cpu"]
        cpu_variant    = core_config.get("cpu_variant", "standard")
-        csr_data_width = core_config.get("csr_data_width", 8)
+        csr_data_width = core_config.get("csr_data_width", 32)
        uart_type      = core_config.get("uart", "rs232")
        if cpu_type is None:
            kwargs["integrated_rom_size"]  = 0