test/reference: update.
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@ -21,9 +21,9 @@
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#define SDRAM_PHY_PHASES 4
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#define SDRAM_PHY_CL 7
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#define SDRAM_PHY_CWL 6
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#define SDRAM_PHY_CMD_LATENCY 1
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#define SDRAM_PHY_RDPHASE 0
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#define SDRAM_PHY_WRPHASE 1
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#define SDRAM_PHY_CMD_LATENCY 0
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#define SDRAM_PHY_RDPHASE 1
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#define SDRAM_PHY_WRPHASE 2
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#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
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#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
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#define SDRAM_PHY_READ_LEVELING_CAPABLE
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@ -21,9 +21,9 @@
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#define SDRAM_PHY_PHASES 4
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#define SDRAM_PHY_CL 9
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#define SDRAM_PHY_CWL 9
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#define SDRAM_PHY_CMD_LATENCY 1
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#define SDRAM_PHY_RDPHASE 2
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#define SDRAM_PHY_WRPHASE 2
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#define SDRAM_PHY_CMD_LATENCY 0
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#define SDRAM_PHY_RDPHASE 3
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#define SDRAM_PHY_WRPHASE 3
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#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
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#define SDRAM_PHY_WRITE_LEVELING_REINIT
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#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
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