phy/model: update DFITimingsChecker to new SDRAMModule timings format
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@ -212,10 +212,10 @@ class DFITimingsChecker(Module):
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if val is None:
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val = 0
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elif key in CK_NS:
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val = self.ck_ns_to_ps(val, tck)
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else:
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elif key == "tCK":
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val = self.ns_to_ps(val)
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else:
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val = self.ck_ns_to_ps(val, tck)
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new_timings[key] = val
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