Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/s7ddrphy: adjust dqs/dq tristate latency. 

OSERDESE2 has a latency of 2 sys_clk.
This commit is contained in:
Florent Kermarrec 2020-10-02 12:15:32 +02:00
parent 6a23bd623b
commit 16480d9aed
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litedram/phy/s7ddrphy.py
View File

@ -206,7 +206,7 @@ class S7DDRPHY(Module, AutoCSR):
dqs_oe = Signal() dqs_oe = Signal()
dqs_preamble = Signal() dqs_preamble = Signal()
dqs_postamble = Signal() dqs_postamble = Signal()
dqs_oe_delay = TappedDelayLine(ntaps=1) dqs_oe_delay = TappedDelayLine(ntaps=2)
dqs_pattern = DQSPattern( dqs_pattern = DQSPattern(
preamble = dqs_preamble, preamble = dqs_preamble,
postamble = dqs_postamble, postamble = dqs_postamble,
@ -298,7 +298,7 @@ class S7DDRPHY(Module, AutoCSR):
# DQ --------------------------------------------------------------------------------------- # DQ ---------------------------------------------------------------------------------------
dq_oe = Signal() dq_oe = Signal()
dq_oe_delay = TappedDelayLine(ntaps=1) dq_oe_delay = TappedDelayLine(ntaps=2)
self.submodules += dq_oe_delay self.submodules += dq_oe_delay
self.comb += dq_oe_delay.input.eq(dqs_preamble | dq_oe | dqs_postamble) self.comb += dq_oe_delay.input.eq(dqs_preamble | dq_oe | dqs_postamble)
for i in range(databits): for i in range(databits):