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modules: adjust MT48LC16M16 timings

This commit is contained in:
Florent Kermarrec 2018-12-27 22:17:57 +01:00
parent 906edf1917
commit 180b3d2cc1
1 changed files with 2 additions and 2 deletions
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4
litedram/modules.py
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@ -121,8 +121,8 @@ class MT48LC16M16(SDRAMModule):
nrows = 8192
ncols = 512
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=14, tRFC=66, tFAW=None, tRAS=None)}
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=66, tFAW=None, tRAS=44)}
class AS4C16M16(SDRAMModule):