test: add test_examples
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@ -50,7 +50,7 @@ class LiteDRAMCrossbar(Module):
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data_width=self.controller.data_width,
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clock_domain="sys",
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id=len(self.masters),
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with_bank=self.controller.settigns.with_reordering)
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with_bank=self.controller.settings.with_reordering)
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self.masters.append(port)
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# clock domain crossing
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@ -0,0 +1,21 @@
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import unittest
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import os
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def build_config(name):
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errors = 0
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os.system("rm -rf examples/build")
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os.system("cd examples && python3 litedram_gen.py {}_config.py".format(name))
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errors += not os.path.isfile("examples/build/gateware/litedram_core.v")
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os.system("rm -rf examples/build")
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return errors
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class TestExamples(unittest.TestCase):
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def test_arty(self):
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errors = build_config("arty")
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self.assertEqual(errors, 0)
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def test_genesys2(self):
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errors = build_config("genesys2")
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self.assertEqual(errors, 0)
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