sdram_init: split init_sequence generation and header geneneration and add .py header genration
This commit is contained in:
Florent Kermarrec
parent
d7d60cf30b
commit
1c083ea9df
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@ -1,59 +1,7 @@
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from migen import log2_int
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def get_sdram_phy_header(sdram_phy_settings):
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
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nphases = sdram_phy_settings.nphases
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r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
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r += "static void cdelay(int i);\n"
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# commands_px functions
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for n in range(nphases):
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r += """
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static void command_p{n}(int cmd)
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{{
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sdram_dfii_pi{n}_command_write(cmd);
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sdram_dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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r += "\n\n"
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# rd/wr access macros
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r += """
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
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r += "\n"
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#
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# sdrrd/sdrwr functions utilities
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#
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r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
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sdram_dfii_pix_wrdata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
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r += """
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const unsigned int sdram_dfii_pix_wrdata_addr[{n}] = {{
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{sdram_dfii_pix_wrdata_addr}
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}};
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""".format(n=nphases, sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
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sdram_dfii_pix_rddata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
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r += """
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const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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{sdram_dfii_pix_rddata_addr}
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}};
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""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
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r += "\n"
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def get_sdram_phy_init_sequence(sdram_phy_settings):
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# init sequence
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cmds = {
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"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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@ -64,6 +12,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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}
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cl = sdram_phy_settings.cl
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mr1 = None
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if sdram_phy_settings.memtype == "SDR":
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bl = 1
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@ -140,6 +89,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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]
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elif sdram_phy_settings.memtype == "DDR3":
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bl = 8
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cwl = sdram_phy_settings.cwl
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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@ -226,24 +176,84 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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z_to_ron[ron],
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z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(
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sdram_phy_settings.cwl,
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cwl,
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z_to_rtt_wr[rtt_wr])
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mr3 = 0
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 2", mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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else:
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raise NotImplementedError("Unsupported memory type: " + sdram_phy_settings.memtype)
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return init_sequence, mr1
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def get_sdram_phy_c_header(sdram_phy_settings):
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
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nphases = sdram_phy_settings.nphases
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r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
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r += "static void cdelay(int i);\n"
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# commands_px functions
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for n in range(nphases):
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r += """
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static void command_p{n}(int cmd)
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{{
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sdram_dfii_pi{n}_command_write(cmd);
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sdram_dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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r += "\n\n"
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# rd/wr access macros
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r += """
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
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r += "\n"
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#
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# sdrrd/sdrwr functions utilities
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#
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r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
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sdram_dfii_pix_wrdata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
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r += """
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const unsigned int sdram_dfii_pix_wrdata_addr[{n}] = {{
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{sdram_dfii_pix_wrdata_addr}
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}};
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""".format(n=nphases, sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
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sdram_dfii_pix_rddata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
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r += """
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const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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{sdram_dfii_pix_rddata_addr}
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}};
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""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
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r += "\n"
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init_sequence, mr1 = get_sdram_phy_init_sequence(sdram_phy_settings)
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if sdram_phy_settings.memtype == "DDR3":
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# the value of MR1 needs to be modified during write leveling
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r += "#define DDR3_MR1 {}\n\n".format(mr1)
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else:
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raise NotImplementedError("Unsupported memory type: "+sdram_phy_settings.memtype)
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r += "static void init_sequence(void)\n{\n"
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for comment, a, ba, cmd, delay in init_sequence:
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@ -262,3 +272,31 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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r += "#endif\n"
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return r
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def get_sdram_phy_py_header(sdram_phy_settings):
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r = ""
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r += "dfii_control_sel = 0x01\n"
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r += "dfii_control_cke = 0x02\n"
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r += "dfii_control_odt = 0x04\n"
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r += "dfii_control_reset_n = 0x08\n"
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r += "\n"
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r += "dfii_command_cs = 0x01\n"
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r += "dfii_command_we = 0x02\n"
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r += "dfii_command_cas = 0x04\n"
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r += "dfii_command_ras = 0x08\n"
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r += "dfii_command_wrdata = 0x10\n"
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r += "dfii_command_rddata = 0x20\n"
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r += "\n"
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init_sequence, _ = get_sdram_phy_init_sequence(sdram_phy_settings)
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r += "init_sequence = [\n"
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for comment, a, ba, cmd, delay in init_sequence:
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r += "(\"" + comment + "\", "
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r += str(a) + ", "
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r += str(ba) + ", "
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r += cmd.lower() + ", "
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r += str(delay) + "),"
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r += "\n"
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r += "]\n"
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return r
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