test: update

This commit is contained in:
Florent Kermarrec 2018-09-06 11:10:20 +02:00
parent 7b61b68f68
commit 1fa73e4718

View file

@ -46,7 +46,7 @@ class DRAMMemory:
pending = 0
elif (yield dram_port.cmd.valid):
pending = not (yield dram_port.cmd.we)
address = (yield dram_port.cmd.adr)
address = (yield dram_port.cmd.addr)
if pending:
yield dram_port.cmd.ready.eq(1)
yield
@ -72,7 +72,7 @@ class DRAMMemory:
yield
elif (yield dram_port.cmd.valid):
pending = (yield dram_port.cmd.we)
address = (yield dram_port.cmd.adr)
address = (yield dram_port.cmd.addr)
if pending:
yield dram_port.cmd.ready.eq(1)
yield