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phy/usddrphy: Add missing iteration on pads.clk when multiple ranks.

This commit is contained in:
Florent Kermarrec 2021-11-29 08:30:59 +01:00
parent 81d318aa46
commit 2113ecfba8
1 changed files with 40 additions and 39 deletions
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79
litedram/phy/usddrphy.py
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@ -137,45 +137,46 @@ class USDDRPHY(Module, AutoCSR):
pads.sel_group(pads_group) pads.sel_group(pads_group)
# Clock -------------------------------------------------------------------------------- # Clock --------------------------------------------------------------------------------
clk_o_nodelay = Signal() for i in range(len(pads.clk_p)):
clk_o_delayed = Signal() clk_o_nodelay = Signal()
self.specials += [ clk_o_delayed = Signal()
Instance("OSERDESE3", self.specials += [
p_SIM_DEVICE = device, Instance("OSERDESE3",
p_DATA_WIDTH = 8, p_SIM_DEVICE = device,
p_INIT = 0, p_DATA_WIDTH = 8,
p_IS_RST_INVERTED = 0, p_INIT = 0,
p_IS_CLK_INVERTED = 0, p_IS_RST_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0, p_IS_CLK_INVERTED = 0,
i_RST = ResetSignal("ic") | self._rst.storage, p_IS_CLKDIV_INVERTED = 0,
i_CLK = ClockSignal("sys4x"), i_RST = ResetSignal("ic") | self._rst.storage,
i_CLKDIV = ClockSignal("sys"), i_CLK = ClockSignal("sys4x"),
i_D = 0b10101010, i_CLKDIV = ClockSignal("sys"),
o_OQ = clk_o_nodelay, i_D = 0b10101010,
), o_OQ = clk_o_nodelay,
Instance("ODELAYE3", ),
p_SIM_DEVICE = device, Instance("ODELAYE3",
p_CASCADE = "NONE", p_SIM_DEVICE = device,
p_UPDATE_MODE = "ASYNC", p_CASCADE = "NONE",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6, p_UPDATE_MODE = "ASYNC",
p_DELAY_FORMAT = "TIME", p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_TYPE = "VARIABLE", p_DELAY_FORMAT = "TIME",
p_DELAY_VALUE = 0, p_DELAY_TYPE = "VARIABLE",
i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage, p_DELAY_VALUE = 0,
i_CLK = ClockSignal("sys"), i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
i_EN_VTC = self._en_vtc.storage, i_CLK = ClockSignal("sys"),
i_CE = self._cdly_inc.re, i_EN_VTC = self._en_vtc.storage,
i_INC = 1, i_CE = self._cdly_inc.re,
o_CNTVALUEOUT = self._cdly_value.status, i_INC = 1,
i_ODATAIN = clk_o_nodelay, o_CNTVALUEOUT = self._cdly_value.status,
o_DATAOUT = clk_o_delayed, i_ODATAIN = clk_o_nodelay,
), o_DATAOUT = clk_o_delayed,
Instance("OBUFDS", ),
i_I = clk_o_delayed, Instance("OBUFDS",
o_O = pads.clk_p, i_I = clk_o_delayed,
o_OB = pads.clk_n, o_O = pads.clk_p[i],
) o_OB = pads.clk_n[i],
] )
]
# Commands ----------------------------------------------------------------------------- # Commands -----------------------------------------------------------------------------
pads_ba = Signal(bankbits) pads_ba = Signal(bankbits)