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frontend/dma/LiteDRAMDMAWriter: Set b.ready to 1 on AXI port.

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Avoid having to do it externally.
This commit is contained in:
Florent Kermarrec 2021-11-26 11:51:49 +01:00
parent 78ff236ca7
commit 81d318aa46
1 changed files with 3 additions and 0 deletions
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3
litedram/frontend/dma.py
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@ -221,6 +221,9 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
wdata.data.eq(fifo.source.data)
]
if is_axi:
self.comb += port.b.ready.eq(1)
if with_csr:
self.add_csr()