Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/usddrphy: Add missing iteration on pads.clk when multiple ranks.

This commit is contained in:
Florent Kermarrec 2021-11-29 08:30:59 +01:00
parent 81d318aa46
commit 2113ecfba8
1 changed files with 40 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
litedram/phy/usddrphy.py
View File

@ -137,45 +137,46 @@ class USDDRPHY(Module, AutoCSR):
pads.sel_group(pads_group)
# Clock --------------------------------------------------------------------------------
clk_o_nodelay = Signal()
clk_o_delayed = Signal()
self.specials += [
Instance("OSERDESE3",
p_SIM_DEVICE = device,
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal("sys"),
i_D = 0b10101010,
o_OQ = clk_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal("sys"),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
o_CNTVALUEOUT = self._cdly_value.status,
i_ODATAIN = clk_o_nodelay,
o_DATAOUT = clk_o_delayed,
),
Instance("OBUFDS",
i_I = clk_o_delayed,
o_O = pads.clk_p,
o_OB = pads.clk_n,
)
]
for i in range(len(pads.clk_p)):
clk_o_nodelay = Signal()
clk_o_delayed = Signal()
self.specials += [
Instance("OSERDESE3",
p_SIM_DEVICE = device,
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal("sys"),
i_D = 0b10101010,
o_OQ = clk_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal("sys"),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
o_CNTVALUEOUT = self._cdly_value.status,
i_ODATAIN = clk_o_nodelay,
o_DATAOUT = clk_o_delayed,
),
Instance("OBUFDS",
i_I = clk_o_delayed,
o_O = pads.clk_p[i],
o_OB = pads.clk_n[i],
)
]
# Commands -----------------------------------------------------------------------------
pads_ba = Signal(bankbits)