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common: allow setting electrical settings with DDR4

This commit is contained in:
Florent Kermarrec 2019-01-08 17:00:51 +01:00
parent fc3a192a87
commit 224a423082
1 changed files with 2 additions and 2 deletions
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4
litedram/common.py
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@ -28,12 +28,12 @@ class PhySettings(Settings):
self.set_attributes(locals())
self.cwl = cl if cwl is None else cwl
# Optional DDR3 electrical settings:
# Optional DDR3/DDR4 electrical settings:
# rtt_nom: Non-Writes on-die termination impedance
# rtt_wr: Writes on-die termination impedance
# ron: Output driver impedance
def add_electrical_settings(self, rtt_nom, rtt_wr, ron):
assert self.memtype == "DDR3"
assert self.memtype in ["DDR3", "DDR4"]
self.set_attributes(locals())