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PhySettings: set missing databits parameter for S6QuarterRateDDRPHY

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Mateusz Holenko 2019-06-13 15:41:47 +02:00
parent 7fbe0b712c
commit 24851c9a3b
1 changed files with 1 additions and 0 deletions
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litedram/phy/s6ddrphy.py
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@ -421,6 +421,7 @@ class S6QuarterRateDDRPHY(Module):
self.settings = PhySettings(
memtype="DDR3",
databits=databits,
dfi_databits=2*databits,
nranks=nranks,
nphases=nphases,