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frontend/dma/LiteDRAMDMAReader: Make sure to flush FIFO/Reservation counter when disabled.

This commit is contained in:
Florent Kermarrec 2022-01-17 10:56:09 +01:00
parent 62abf9ce0c
commit 24fad45764
1 changed files with 7 additions and 4 deletions
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11
litedram/frontend/dma.py
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@ -54,6 +54,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
def __init__(self, port, fifo_depth=16, fifo_buffered=False, with_csr=False): def __init__(self, port, fifo_depth=16, fifo_buffered=False, with_csr=False):
assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort)) assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
self.port = port self.port = port
self.enable = enable = Signal(reset=1)
self.sink = sink = stream.Endpoint([("address", port.address_width)]) self.sink = sink = stream.Endpoint([("address", port.address_width)])
self.source = source = stream.Endpoint([("data", port.data_width)]) self.source = source = stream.Endpoint([("data", port.data_width)])
@ -79,8 +80,8 @@ class LiteDRAMDMAReader(Module, AutoCSR):
self.comb += cmd.size.eq(int(log2(port.data_width//8))) self.comb += cmd.size.eq(int(log2(port.data_width//8)))
self.comb += [ self.comb += [
cmd.addr.eq(sink.address), cmd.addr.eq(sink.address),
cmd.valid.eq(sink.valid & request_enable), cmd.valid.eq(enable & sink.valid & request_enable),
sink.ready.eq(cmd.ready & request_enable), sink.ready.eq(enable & cmd.ready & request_enable),
request_issued.eq(cmd.valid & cmd.ready) request_issued.eq(cmd.valid & cmd.ready)
] ]
@ -104,8 +105,9 @@ class LiteDRAMDMAReader(Module, AutoCSR):
self.comb += [ self.comb += [
rdata.connect(fifo.sink, omit={"id", "resp"}), rdata.connect(fifo.sink, omit={"id", "resp"}),
fifo.source.connect(source), fifo.source.connect(source, omit={"ready"}),
data_dequeued.eq(source.valid & source.ready) fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled.
data_dequeued.eq(fifo.source.valid & fifo.source.ready)
] ]
if with_csr: if with_csr:
@ -125,6 +127,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
base = Signal(self.port.address_width) base = Signal(self.port.address_width)
offset = Signal(self.port.address_width) offset = Signal(self.port.address_width)
length = Signal(self.port.address_width) length = Signal(self.port.address_width)
self.comb += self.enable.eq(self._enable.storage)
self.comb += base.eq(self._base.storage[shift:]) self.comb += base.eq(self._base.storage[shift:])
self.comb += length.eq(self._length.storage[shift:]) self.comb += length.eq(self._length.storage[shift:])