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frontend/adaptation: adapt fifo depths

This commit is contained in:
Florent Kermarrec 2016-06-02 22:35:27 +02:00
parent 0faee6639d
commit 25c5a8aaf5
1 changed files with 3 additions and 3 deletions
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6
litedram/frontend/adaptation.py
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@ -18,7 +18,7 @@ class LiteDRAMPortCDC(Module):
# # # # # #
cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 8) cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 4)
cmd_fifo = ClockDomainsRenamer({"write": cd_from, cmd_fifo = ClockDomainsRenamer({"write": cd_from,
"read": cd_to})(cmd_fifo) "read": cd_to})(cmd_fifo)
self.submodules += cmd_fifo self.submodules += cmd_fifo
@ -27,7 +27,7 @@ class LiteDRAMPortCDC(Module):
cmd_fifo.source.connect(port_to.cmd) cmd_fifo.source.connect(port_to.cmd)
] ]
wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 8) wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 16)
wdata_fifo = ClockDomainsRenamer({"write": cd_from, wdata_fifo = ClockDomainsRenamer({"write": cd_from,
"read": cd_to})(wdata_fifo) "read": cd_to})(wdata_fifo)
self.submodules += wdata_fifo self.submodules += wdata_fifo
@ -36,7 +36,7 @@ class LiteDRAMPortCDC(Module):
wdata_fifo.source.connect(port_to.wdata) wdata_fifo.source.connect(port_to.wdata)
] ]
rdata_fifo = stream.AsyncFIFO([("data", dw)], 8) rdata_fifo = stream.AsyncFIFO([("data", dw)], 16)
rdata_fifo = ClockDomainsRenamer({"write": cd_to, rdata_fifo = ClockDomainsRenamer({"write": cd_to,
"read": cd_from})(rdata_fifo) "read": cd_from})(rdata_fifo)
self.submodules += rdata_fifo self.submodules += rdata_fifo