frontend/adaptation: adapt fifo depths
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@ -18,7 +18,7 @@ class LiteDRAMPortCDC(Module):
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# # #
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cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 8)
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cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 4)
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cmd_fifo = ClockDomainsRenamer({"write": cd_from,
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"read": cd_to})(cmd_fifo)
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self.submodules += cmd_fifo
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@ -27,7 +27,7 @@ class LiteDRAMPortCDC(Module):
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cmd_fifo.source.connect(port_to.cmd)
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]
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wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 8)
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wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 16)
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wdata_fifo = ClockDomainsRenamer({"write": cd_from,
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"read": cd_to})(wdata_fifo)
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self.submodules += wdata_fifo
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@ -36,7 +36,7 @@ class LiteDRAMPortCDC(Module):
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wdata_fifo.source.connect(port_to.wdata)
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]
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rdata_fifo = stream.AsyncFIFO([("data", dw)], 8)
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rdata_fifo = stream.AsyncFIFO([("data", dw)], 16)
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rdata_fifo = ClockDomainsRenamer({"write": cd_to,
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"read": cd_from})(rdata_fifo)
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self.submodules += rdata_fifo
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