phy/usddrphy/Clk: Connect cdly_value only on first clk pad.

2025-01-04 09:52:25 -05:00 · 2022-05-02 17:34:52 +02:00 · 2022-05-02 17:34:52 +02:00 · 2b8af870c5
commit 2b8af870c5
parent 692355d120
1 changed files with 1 additions and 1 deletions
--- a/litedram/phy/usddrphy.py
+++ b/litedram/phy/usddrphy.py
@ -167,7 +167,7 @@ class USDDRPHY(Module, AutoCSR):
                        i_EN_VTC       = self._en_vtc.storage,
                        i_CE           = self._cdly_inc.re,
                        i_INC          = 1,
-                        o_CNTVALUEOUT  = self._cdly_value.status,
+                        o_CNTVALUEOUT  = self._cdly_value.status if i == 0 else Signal(),
                        i_ODATAIN      = clk_o_nodelay,
                        o_DATAOUT      = clk_o_delayed,
                    ),