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core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut)

This commit is contained in:
Florent Kermarrec 2018-08-15 15:49:11 +02:00
parent 6d234219b4
commit 2e362ee160
2 changed files with 28 additions and 14 deletions
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38
litedram/core/bankmachine.py
View File

@ -43,14 +43,25 @@ class BankMachine(Module):
# Command buffer # Command buffer
cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))] cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth) if settings.with_auto_precharge:
cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
self.submodules += cmd_buffer_lookahead, cmd_buffer cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
self.submodules += cmd_buffer_lookahead, cmd_buffer
self.comb += [
req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready",
"rdata_valid", "rdata_ready",
"lock"]),
cmd_buffer_lookahead.source.connect(cmd_buffer.sink)
]
else:
cmd_buffer = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
self.submodules += cmd_buffer
self.comb += [
req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready",
"rdata_valid", "rdata_ready",
"lock"])
]
self.comb += [ self.comb += [
req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready",
"rdata_valid", "rdata_ready",
"lock"]),
cmd_buffer_lookahead.source.connect(cmd_buffer.sink),
cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid), cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
req.lock.eq(cmd_buffer.source.valid), req.lock.eq(cmd_buffer.source.valid),
] ]
@ -91,13 +102,14 @@ class BankMachine(Module):
cmd.is_write)) cmd.is_write))
# Auto Precharge # Auto Precharge
self.comb += [ if settings.with_auto_precharge:
If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid, self.comb += [
If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr), If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid,
auto_precharge.eq(self.precharge_timer.done & (track_close == 0)) If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr),
auto_precharge.eq(self.precharge_timer.done & (track_close == 0))
)
) )
) ]
]
# Control and command generation FSM # Control and command generation FSM
# Note: tRRD, tFAW, tCCD, tWTR timings are enforced by the multiplexer # Note: tRRD, tFAW, tCCD, tWTR timings are enforced by the multiplexer

4
litedram/core/controller.py
View File

@ -10,12 +10,14 @@ from litedram.core.multiplexer import *
class ControllerSettings: class ControllerSettings:
def __init__(self, cmd_buffer_depth=8, read_time=32, write_time=16, def __init__(self, cmd_buffer_depth=8, read_time=32, write_time=16,
with_bandwidth=False, with_bandwidth=False,
with_refresh=True): with_refresh=True,
with_auto_precharge=False):
self.cmd_buffer_depth = cmd_buffer_depth self.cmd_buffer_depth = cmd_buffer_depth
self.read_time = read_time self.read_time = read_time
self.write_time = write_time self.write_time = write_time
self.with_bandwidth = with_bandwidth self.with_bandwidth = with_bandwidth
self.with_refresh = with_refresh self.with_refresh = with_refresh
self.with_auto_precharge = with_auto_precharge
class LiteDRAMController(Module): class LiteDRAMController(Module):