core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut)
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6d234219b4
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@ -43,6 +43,7 @@ class BankMachine(Module):
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# Command buffer
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cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
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if settings.with_auto_precharge:
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cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
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cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
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self.submodules += cmd_buffer_lookahead, cmd_buffer
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@ -50,7 +51,17 @@ class BankMachine(Module):
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req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready",
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"rdata_valid", "rdata_ready",
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"lock"]),
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cmd_buffer_lookahead.source.connect(cmd_buffer.sink),
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cmd_buffer_lookahead.source.connect(cmd_buffer.sink)
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]
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else:
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cmd_buffer = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
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self.submodules += cmd_buffer
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self.comb += [
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req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready",
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"rdata_valid", "rdata_ready",
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"lock"])
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]
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self.comb += [
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cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
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req.lock.eq(cmd_buffer.source.valid),
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]
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@ -91,6 +102,7 @@ class BankMachine(Module):
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cmd.is_write))
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# Auto Precharge
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if settings.with_auto_precharge:
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self.comb += [
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If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid,
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If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr),
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@ -10,12 +10,14 @@ from litedram.core.multiplexer import *
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class ControllerSettings:
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def __init__(self, cmd_buffer_depth=8, read_time=32, write_time=16,
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with_bandwidth=False,
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with_refresh=True):
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with_refresh=True,
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with_auto_precharge=False):
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self.cmd_buffer_depth = cmd_buffer_depth
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self.read_time = read_time
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self.write_time = write_time
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self.with_bandwidth = with_bandwidth
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self.with_refresh = with_refresh
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self.with_auto_precharge = with_auto_precharge
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class LiteDRAMController(Module):
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