bench: simplify/improve, working on arty/genesys2.
This commit is contained in:
Florent Kermarrec
parent
5c69da5d6d
commit
2e3e19e9d4
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@ -40,7 +40,7 @@ class _CRG(Module, AutoCSR):
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self.submodules.main_pll = main_pll = S7PLL(speedgrade=-1)
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self.comb += main_pll.reset.eq(~platform.request("cpu_reset"))
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main_pll.register_clkin(platform.request("clk100"), 100e6)
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main_pll.create_clkout(self.cd_sys_pll, 100e6)
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main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
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main_pll.create_clkout(self.cd_clk200, 200e6)
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main_pll.create_clkout(self.cd_eth, 25e6)
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main_pll.expose_drp()
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@ -54,7 +54,7 @@ class _CRG(Module, AutoCSR):
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~main_pll.locked)
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pll.register_clkin(self.cd_sys_pll.clk, 100e6)
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pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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@ -62,7 +62,7 @@ class _CRG(Module, AutoCSR):
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6)):
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def __init__(self, sys_clk_freq=int(150e6)):
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platform = arty.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -98,12 +98,14 @@ class BenchSoC(SoCCore):
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.submodules.led = LedChaser(self.platform.request_all("user_led"), sys_clk_freq)
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self.add_csr("led")
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Bench Test ---------------------------------------------------------------------------------------
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def bench_test():
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def bench_test(vco_freq):
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import time
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from litex import RemoteClient
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@ -122,7 +124,7 @@ def bench_test():
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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wb.write(wb.mems.rom.base + 4*i)
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wb.write(wb.mems.rom.base + 4*i, data)
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class ClkReg1:
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def __init__(self, value=0):
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@ -204,21 +206,17 @@ def bench_test():
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ctrl = SoCCtrl()
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ctrl.load_rom("build/arty/software/bios/bios.bin")
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ctrl.reset()
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vco_freq = 1.6e9
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ctrl.reboot()
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s7pll = S7PLL()
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print("Dump Main PLL...")
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x08))
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print(clkout0_clkreg1)
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for i in range(12, 44, 2):
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sys_clk_freq = vco_freq/i
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print("Reconfig Main PLL to {}MHz...".format(sys_clk_freq/1e6))
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clkout0_clkreg1.high_time = i//2 + i%2
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clkout0_clkreg1.low_time = i//2
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for clk_freq in range(int(60e6), int(150e6), int(10e6)):
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vco_div = int(vco_freq/clk_freq)
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print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6))
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clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
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clkout0_clkreg1.low_time = vco_div//2
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s7pll.write(0x08, clkout0_clkreg1.pack())
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print("Measuring sys_clk...")
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@ -228,8 +226,8 @@ def bench_test():
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end = wb.regs.crg_sys_clk_counter.read()
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print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration)))
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print("Reset SoC and get BIOS log...")
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ctrl.reset()
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print("Reboot SoC and get BIOS log...")
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ctrl.reboot()
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start = time.time()
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while (time.time() - start) < 5:
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if wb.regs.uart_xover_rxempty.read() == 0:
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@ -248,7 +246,6 @@ def main():
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parser.add_argument("--test", action="store_true", help="Run Test")
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args = parser.parse_args()
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if args.build or args.load:
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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@ -258,7 +255,7 @@ def main():
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.test:
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bench_test()
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bench_test(vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if __name__ == "__main__":
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main()
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@ -38,24 +38,26 @@ class _CRG(Module, AutoCSR):
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self.submodules.main_pll = main_pll = S7PLL(speedgrade=-2)
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self.comb += main_pll.reset.eq(~platform.request("cpu_reset_n"))
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main_pll.register_clkin(platform.request("clk200"), 200e6)
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main_pll.create_clkout(self.cd_sys_pll, 200e6)
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main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
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main_pll.create_clkout(self.cd_clk200, 200e6)
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main_pll.expose_drp()
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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sys_clk_counter = Signal(32)
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self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
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self.sys_clk_counter = CSRStatus(32)
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self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
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self.submodules.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(~main_pll.locked)
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pll.register_clkin(self.cd_sys_pll.clk, 200e6)
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pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6)):
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def __init__(self, sys_clk_freq=int(175e6)):
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platform = genesys2.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -97,7 +99,7 @@ class BenchSoC(SoCCore):
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# Bench Test ---------------------------------------------------------------------------------------
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def bench_test():
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def bench_test(vco_freq):
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import time
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from litex import RemoteClient
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@ -116,7 +118,7 @@ def bench_test():
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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wb.write(wb.mems.rom.base + 4*i)
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wb.write(wb.mems.rom.base + 4*i, data)
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class ClkReg1:
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def __init__(self, value=0):
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@ -198,21 +200,17 @@ def bench_test():
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ctrl = SoCCtrl()
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ctrl.load_rom("build/genesys2/software/bios/bios.bin")
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ctrl.reset()
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vco_freq = 1.8e9
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ctrl.reboot()
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s7pll = S7PLL()
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print("Dump Main PLL...")
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x08))
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print(clkout0_clkreg1)
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for i in range(7, 14):
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sys_clk_freq = (125e6/200e6)*(vco_freq/i)
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print("Reconfig Main PLL to {}MHz...".format(sys_clk_freq/1e6))
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clkout0_clkreg1.high_time = i//2 + i%2
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clkout0_clkreg1.low_time = i//2
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for clk_freq in range(int(60e6), int(180e6), int(10e6)):
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vco_div = int(vco_freq/clk_freq)
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print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6))
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clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
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clkout0_clkreg1.low_time = vco_div//2
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s7pll.write(0x08, clkout0_clkreg1.pack())
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print("Measuring sys_clk...")
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@ -222,8 +220,8 @@ def bench_test():
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end = wb.regs.crg_sys_clk_counter.read()
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print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration)))
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print("Reset SoC and get BIOS log...")
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ctrl.reset()
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print("Reboot SoC and get BIOS log...")
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ctrl.reboot()
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start = time.time()
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while (time.time() - start) < 5:
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if wb.regs.uart_xover_rxempty.read() == 0:
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@ -242,7 +240,6 @@ def main():
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parser.add_argument("--test", action="store_true", help="Run Test")
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args = parser.parse_args()
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if args.build or args.load:
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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@ -252,7 +249,7 @@ def main():
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.test:
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bench_test()
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bench_test(vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if __name__ == "__main__":
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main()
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@ -73,6 +73,7 @@ class BenchSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# DDR4 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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@ -88,7 +89,7 @@ class BenchSoC(SoCCore):
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size = 0x40000000,
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)
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# Ethebone ---------------------------------------------------------------------------------
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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@ -105,7 +106,7 @@ class BenchSoC(SoCCore):
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# Bench Test ---------------------------------------------------------------------------------------
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def bench_test():
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def bench_test(sys_clk_freq, vco_freq):
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import time
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from litex import RemoteClient
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@ -124,7 +125,7 @@ def bench_test():
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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wb.write(wb.mems.rom.base + 4*i)
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wb.write(wb.mems.rom.base + 4*i, data)
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class ClkReg1:
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def __init__(self, value=0):
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@ -206,20 +207,16 @@ def bench_test():
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ctrl = SoCCtrl()
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ctrl.load_rom("build/kcu105/software/bios/bios.bin")
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ctrl.reset()
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vco_freq = 1e9
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ctrl.reboot()
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uspll = USPLL()
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print("Dump Main PLL...")
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clkout0_clkreg1 = ClkReg1(uspll.read(0x08))
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print(clkout0_clkreg1)
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x08))
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# TODO: add dynamic freq test.
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print("Reset SoC and get BIOS log...")
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ctrl.reset()
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print("Reboot SoC and get BIOS log...")
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ctrl.reboot()
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start = time.time()
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while (time.time() - start) < 5:
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if wb.regs.uart_xover_rxempty.read() == 0:
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@ -238,7 +235,6 @@ def main():
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parser.add_argument("--test", action="store_true", help="Run Test")
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args = parser.parse_args()
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if args.build or args.load:
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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@ -248,7 +244,7 @@ def main():
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.test:
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bench_test()
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bench_test(vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if __name__ == "__main__":
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main()
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