Hardware/litedram
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litedram.git synced 2025-01-04 09:52:25 -05:00
Code Issues Projects Releases Packages Wiki Activity

test/test_ecc: Update.

Browse source
This commit is contained in:
Florent Kermarrec 2021-06-08 15:07:39 +02:00
parent 8b606cd05a
commit 2fcc6fe552
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
test/test_ecc.py
View file

@ -88,6 +88,7 @@ class TestECC(unittest.TestCase):
def __init__(self):
eccw = LiteDRAMNativePortECCW(data_width_from=32*8, data_width_to=39*8)
self.submodules.eccw = eccw
self.comb += eccw.sink.we.eq(2**(32*8)-1)
def main_generator(dut):
yield
@ -179,6 +180,7 @@ class TestECC(unittest.TestCase):
yield port.cmd.valid.eq(0)
yield
yield port.wdata.valid.eq(1)
yield port.wdata.we.eq(2**from_width-1)
yield port.wdata.data.eq(dut.wdata[i])
yield
while (yield port.wdata.ready) == 0: