core/refresher: use self.sync to fix build (verilog wire vs reg...)

2025-01-04 09:52:25 -05:00 · 2018-12-07 17:46:43 +01:00 · 2018-12-07 17:46:43 +01:00 · 33ff34b622
commit 33ff34b622
parent 8419f2846d
1 changed files with 1 additions and 1 deletions
--- a/litedram/core/refresher.py
+++ b/litedram/core/refresher.py
@ -35,7 +35,7 @@ class RefreshGenerator(Module):
                ])
            ])
        ]
-        self.comb += [
+        self.sync += [
            cmd.a.eq(2**10),
            cmd.ba.eq(0),
            cmd.cas.eq(0),