core/bankmachine: add Four Activate Window support (tFAW)
This commit is contained in:
Florent Kermarrec
parent
d0ff536e0d
commit
370b05ecf1
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@ -31,13 +31,14 @@ class GeomSettings:
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class TimingSettings:
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def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC):
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def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW):
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self.tRP = tRP
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self.tRCD = tRCD
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self.tWR = tWR
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self.tWTR = tWTR
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self.tREFI = tREFI
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self.tRFC = tRFC
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self.tFAW = tFAW
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def cmd_layout(aw):
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@ -37,8 +37,6 @@ class BankMachine(Module):
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# # #
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auto_precharge = Signal()
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slicer = _AddressSlicer(settings.geom.colbits, address_align)
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# Command buffer
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@ -71,6 +69,7 @@ class BankMachine(Module):
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)
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# Auto Precharge
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auto_precharge = Signal()
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self.comb += [
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# If both buffers have data to output, check row to see
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# if we can embed an autoprecharge in current cmd.
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@ -81,6 +80,20 @@ class BankMachine(Module):
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)
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]
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# Four Activate Window
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activate = Signal()
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activate_allowed = Signal(reset=1)
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tfaw = settings.timing.tFAW
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if tfaw is not None:
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activate_count = Signal(max=tfaw)
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activate_window = Signal(tfaw)
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self.sync += activate_window.eq(Cat(activate, activate_window))
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for i in range(tfaw):
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next_activate_count = Signal(max=tfaw)
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self.comb += next_activate_count.eq(activate_count + activate_window[i])
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activate_count = next_activate_count
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self.comb += If(activate_count >=4, activate_allowed.eq(0))
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# Address generation
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sel_row_adr = Signal()
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self.comb += [
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@ -126,7 +139,9 @@ class BankMachine(Module):
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NextState("PRECHARGE")
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)
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).Else(
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NextState("ACTIVATE")
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If(activate_allowed,
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NextState("ACTIVATE")
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)
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)
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)
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)
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@ -151,6 +166,7 @@ class BankMachine(Module):
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track_close.eq(1)
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)
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fsm.act("ACTIVATE",
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activate.eq(1),
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sel_row_adr.eq(1),
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track_open.eq(1),
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cmd.valid.eq(1),
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@ -4,6 +4,9 @@ from migen import *
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from litedram.common import GeomSettings, TimingSettings
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# TODO:
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# - add speedgrade support
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# - specify tWTR, tFAW in ck or ns
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class SDRAMModule:
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def __init__(self, clk_freq, rate):
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@ -18,9 +21,10 @@ class SDRAMModule:
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tRP=self.ns(self.tRP),
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tRCD=self.ns(self.tRCD),
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tWR=self.ns(self.tWR),
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tWTR=self.tWTR,
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tREFI=self.ns(self.tREFI, False),
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tRFC=self.ns(self.tRFC)
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tRFC=self.ns(self.tRFC),
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tWTR=self.tWTR,
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tFAW=None if not hasattr(self, "tFAW") else self.tFAW
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)
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def ns(self, t, margin=True):
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@ -42,13 +46,15 @@ class IS42S16160(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings (-7 speedgrade)
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# timings (ns)
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tRP = 20
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tRCD = 20
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tWR = 20
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 70
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class MT48LC4M16(SDRAMModule):
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@ -57,13 +63,15 @@ class MT48LC4M16(SDRAMModule):
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nbanks = 4
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nrows = 4096
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ncols = 256
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# timings (-7 speedgrade)
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 14
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tWTR = 2
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tREFI = 64*1000*1000/4096
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tRFC = 66
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class AS4C16M16(SDRAMModule):
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@ -72,13 +80,16 @@ class AS4C16M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings (-6 speedgrade)
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# timings (ns)
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tRP = 18
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tRCD = 18
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tWR = 12
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 60
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# DDR
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@ -88,13 +99,15 @@ class MT46V32M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings (-6 speedgrade)
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 70
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# LPDDR
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@ -104,13 +117,15 @@ class MT46H32M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 72
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class MT46H32M32(SDRAMModule):
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memtype = "LPDDR"
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@ -118,13 +133,15 @@ class MT46H32M32(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 72
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# DDR2
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@ -134,13 +151,15 @@ class MT47H128M8(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 7800
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tRFC = 127.5
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class MT47H64M16(SDRAMModule):
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@ -149,13 +168,15 @@ class MT47H64M16(SDRAMModule):
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 7800
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tRFC = 127.5
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class P3R1GE4JGF(SDRAMModule):
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@ -164,14 +185,15 @@ class P3R1GE4JGF(SDRAMModule):
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 12.5
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tRCD = 12.5
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tWR = 15
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tWTR = 3
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tREFI = 7800
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tRFC = 127.5
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = None
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# DDR3
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class MT8JTF12864(SDRAMModule):
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@ -180,13 +202,15 @@ class MT8JTF12864(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 7800
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tRFC = 70
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = ceil(32/4)
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class MT41J128M16(SDRAMModule):
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@ -195,13 +219,15 @@ class MT41J128M16(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 3
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tREFI = 64*1000*1000/16384
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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class MT41K128M16(SDRAMModule):
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@ -210,13 +236,15 @@ class MT41K128M16(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings (-7 speedgrade)
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tWTR = 3
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tREFI = 64*1000*1000/8192
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tRFC = 160
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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class MT41K256M16(SDRAMModule):
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@ -225,13 +253,15 @@ class MT41K256M16(SDRAMModule):
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nbanks = 8
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nrows = 32768
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ncols = 1024
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# timings (-7 speedgrade)
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tWTR = 3
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tREFI = 64*1000*1000/8192
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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class MT41J256M16(SDRAMModule):
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@ -240,13 +270,15 @@ class MT41J256M16(SDRAMModule):
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nbanks = 8
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nrows = 32768
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ncols = 1024
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# timings (-125 speedgrade)
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tWTR = 3
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tREFI = 64*1000*1000/8192
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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class MT18KSF1G72HZ_1G6(SDRAMModule):
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@ -255,10 +287,12 @@ class MT18KSF1G72HZ_1G6(SDRAMModule):
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nbanks = 8
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nrows = 65536
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ncols = 1024
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# timings (-125 speedgrade)
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tWTR = 3
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tREFI = 64*1000*1000/8192
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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