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modules: Add AS4C32M16 32Mx16 SDRAM 

Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2018-11-05 12:26:20 +00:00
parent 82c08c78c9
commit 3a5d45bd5e
1 changed files with 11 additions and 0 deletions
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11
litedram/modules.py
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@ -136,6 +136,17 @@ class AS4C16M16(SDRAMModule):
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
class AS4C32M16(SDRAMModule):
memtype = "SDR"
# geometry
nbanks = 4
nrows = 8192
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
# DDR # DDR
class MT46V32M16(SDRAMModule): class MT46V32M16(SDRAMModule):
memtype = "DDR" memtype = "DDR"