init: Cleanup PHY lists in capabilities.
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@ -685,13 +685,16 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
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r += "#define SDRAM_PHY_WRPHASE "+str(wrphase)+"\n"
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r += "#define SDRAM_PHY_WRPHASE "+str(wrphase)+"\n"
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# Define Read/Write Leveling capability
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# Define Read/Write Leveling capability
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if phytype in ["USDDRPHY", "USPDDRPHY", 'K7DDRPHY', 'V7DDRPHY', 'K7LPDDR4PHY', 'V7LPDDR4PHY']:
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if phytype in ["USDDRPHY", "USPDDRPHY",
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"K7DDRPHY", "V7DDRPHY",
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"K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
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r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
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if phytype in ["USDDRPHY", "USPDDRPHY", 'A7DDRPHY', 'K7DDRPHY', 'V7DDRPHY', 'A7LPDDR4PHY',
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if phytype in ["USDDRPHY", "USPDDRPHY",
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'K7LPDDR4PHY', 'V7LPDDR4PHY']:
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"A7DDRPHY", "K7DDRPHY", "V7DDRPHY",
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"A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
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r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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if phytype in ['K7LPDDR4PHY', 'V7LPDDR4PHY']:
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if phytype in ["K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
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r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
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if phytype in ["ECP5DDRPHY"]:
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if phytype in ["ECP5DDRPHY"]:
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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