phy: BitSlip now integrated in LiteX

litedram/phy/bitslip.py

@@ -1,17 +0,0 @@
-from litex.gen import *
-
-
-class BitSlip(Module):
-    def __init__(self, dw):
-        self.i = Signal(dw)
-        self.o = Signal(dw)
-        self.value = Signal(max=dw)
-
-        # # #
-
-        r = Signal(2*dw)
-        self.sync += r.eq(Cat(r[dw:], self.i))
-        cases = {}
-        for i in range(dw):
-            cases[i] = self.o.eq(r[i:dw+i])
-        self.sync += Case(self.value, cases)

litedram/phy/kusddrphy.py

@@ -2,12 +2,12 @@
 # tCK=5ns CL=7 CWL=6
 
 from litex.gen import *
+from litex.gen.genlib.misc import BitSlip
 
 from litex.soc.interconnect.csr import *
 
 from litedram.common import PhySettings
 from litedram.phy.dfi import *
-from litedram.phy.bitslip import BitSlip
 
 # TODO:
 # - verify read_latency in simulation (OSERDESE3/ISERDESE3)