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test: also test reads on downconverter/upconverter

This commit is contained in:
Florent Kermarrec 2016-05-24 21:40:46 +02:00
parent 32a6e25021
commit 3fe3a843e0
3 changed files with 37 additions and 9 deletions
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9
test/common.py
View File

@ -14,8 +14,8 @@ class DRAMMemory:
def read_generator(self, dram_port):
address = 0
pending = 0
while True:
yield dram_port.cmd.ready.eq(0)
while True:
yield dram_port.rdata.valid.eq(0)
if pending:
yield dram_port.rdata.valid.eq(1)
@ -27,16 +27,18 @@ class DRAMMemory:
elif (yield dram_port.cmd.valid):
pending = not (yield dram_port.cmd.we)
address = (yield dram_port.cmd.adr)
yield
if pending:
yield dram_port.cmd.ready.eq(1)
yield
yield dram_port.cmd.ready.eq(0)
yield
@passive
def write_generator(self, dram_port):
address = 0
pending = 0
while True:
yield dram_port.cmd.ready.eq(0)
while True:
yield dram_port.wdata.ready.eq(0)
if pending:
yield dram_port.wdata.ready.eq(1)
@ -49,6 +51,7 @@ class DRAMMemory:
elif (yield dram_port.cmd.valid):
pending = (yield dram_port.cmd.we)
address = (yield dram_port.cmd.adr)
if pending:
yield dram_port.cmd.ready.eq(1)
yield
yield dram_port.cmd.ready.eq(0)

14
test/downconverter_tb.py
View File

@ -30,12 +30,24 @@ def main_generator(dut):
while (yield dut.user_port.wdata.ready) == 0:
yield
yield
# read
yield dut.user_port.rdata.ready.eq(1)
for i in range(8):
yield dut.user_port.cmd.valid.eq(1)
yield dut.user_port.cmd.we.eq(0)
yield dut.user_port.cmd.adr.eq(i)
yield
while (yield dut.user_port.cmd.ready) == 0:
yield
yield dut.user_port.cmd.valid.eq(0)
yield
if __name__ == "__main__":
tb = TB()
generators = {
"sys" : [main_generator(tb),
tb.memory.write_generator(tb.internal_port)]
tb.memory.write_generator(tb.internal_port),
tb.memory.read_generator(tb.internal_port)]
}
clocks = {"sys": 10}
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")

15
test/upconverter_tb.py
View File

@ -37,12 +37,25 @@ def main_generator(dut):
yield
yield dut.user_port.wdata.valid.eq(0)
yield
# read
for i in range(8):
yield dut.user_port.rdata.ready.eq(1)
for j in range(2):
yield dut.user_port.cmd.valid.eq(1)
yield dut.user_port.cmd.we.eq(0)
yield dut.user_port.cmd.adr.eq(i)
yield
while (yield dut.user_port.cmd.ready) == 0:
yield
yield dut.user_port.cmd.valid.eq(0)
yield
if __name__ == "__main__":
tb = TB()
generators = {
"sys" : [main_generator(tb),
tb.memory.write_generator(tb.internal_port)]
tb.memory.write_generator(tb.internal_port),
tb.memory.read_generator(tb.internal_port)]
}
clocks = {"sys": 10}
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")