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test: update *_init.h reference

This commit is contained in:
Jędrzej Boczar 2021-06-28 15:37:42 +02:00
parent 377746bfd8
commit 43036c9576
3 changed files with 96 additions and 87 deletions
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13
test/reference/ddr3_init.h
View File

@ -1,5 +1,6 @@
#ifndef __GENERATED_SDRAM_PHY_H
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
@ -26,8 +27,8 @@
#define SDRAM_PHY_RDPHASE 1
#define SDRAM_PHY_WRPHASE 2
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
#define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
#define SDRAM_PHY_DELAYS 32
@ -58,7 +59,8 @@ __attribute__((unused)) static inline void command_p3(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
@ -67,8 +69,8 @@ static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
default: return 0;
}
}
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
@ -124,4 +126,5 @@ static inline void init_sequence(void)
cdelay(200);
}
#endif
#endif /* __GENERATED_SDRAM_PHY_H */

11
test/reference/ddr4_init.h
View File

@ -1,5 +1,6 @@
#ifndef __GENERATED_SDRAM_PHY_H
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
@ -57,7 +58,8 @@ __attribute__((unused)) static inline void command_p3(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
@ -66,8 +68,8 @@ static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
default: return 0;
}
}
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
@ -138,4 +140,5 @@ static inline void init_sequence(void)
cdelay(200);
}
#endif
#endif /* __GENERATED_SDRAM_PHY_H */

11
test/reference/sdr_init.h
View File

@ -1,5 +1,6 @@
#ifndef __GENERATED_SDRAM_PHY_H
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
@ -36,14 +37,15 @@ __attribute__((unused)) static inline void command_p0(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
default: return 0;
}
}
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
default: return 0;
@ -93,4 +95,5 @@ static inline void init_sequence(void)
cdelay(200);
}
#endif
#endif /* __GENERATED_SDRAM_PHY_H */