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bench/kcu105/xcu1525: Also use PHYPadsReducer to easily test various DFI sizes.

This commit is contained in:
Florent Kermarrec 2021-07-13 14:57:42 +02:00
parent fd8d6f8334
commit 4326fe7f36
2 changed files with 7 additions and 3 deletions
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6
bench/kcu105.py
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@ -19,8 +19,9 @@ from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.modules import EDY4016A from litedram.common import PHYPadsReducer
from litedram.phy import usddrphy from litedram.phy import usddrphy
from litedram.modules import EDY4016A
from liteeth.phy.ku_1000basex import KU_1000BASEX from liteeth.phy.ku_1000basex import KU_1000BASEX
@ -91,7 +92,8 @@ class BenchSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM ------------------------------------------------------------------------------- # DDR4 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), self.submodules.ddrphy = usddrphy.USDDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6)

4
bench/xcu1525.py
View File

@ -19,6 +19,7 @@ from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.common import PHYPadsReducer
from litedram.modules import MT40A512M8 from litedram.modules import MT40A512M8
from litedram.phy import usddrphy from litedram.phy import usddrphy
@ -87,7 +88,8 @@ class BenchSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq, channel) self.submodules.crg = _CRG(platform, sys_clk_freq, channel)
# DDR4 SDRAM ------------------------------------------------------------------------------- # DDR4 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", channel), self.submodules.ddrphy = usddrphy.USPDDRPHY(
pads = PHYPadsReducer(platform.request("ddram", channel), [0, 1, 2, 3, 4, 5, 6, 7]),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6) iodelay_clk_freq = 500e6)