uniformize litex cores
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__pycache__
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# Byte-compiled / optimized / DLL files
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*.pyc
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__pycache__/
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*.egg-info
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*.py[cod]
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*.vcd
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*$py.class
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outgoing
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# C extensions
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*.so
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# Distribution / packaging
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.Python
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env/
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build/
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develop-eggs/
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dist/
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downloads/
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eggs/
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.eggs/
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lib/
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lib64/
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parts/
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sdist/
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var/
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*.egg-info/
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.installed.cfg
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*.egg
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# PyInstaller
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# Usually these files are written by a python script from a template
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# before PyInstaller builds the exe, so as to inject date/other infos into it.
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*.manifest
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*.spec
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# Installer logs
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pip-log.txt
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pip-delete-this-directory.txt
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# Unit test / coverage reports
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htmlcov/
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.tox/
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.coverage
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.coverage.*
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.cache
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nosetests.xml
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coverage.xml
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*,cover
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.hypothesis/
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# Translations
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*.mo
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*.pot
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# Django stuff:
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*.log
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local_settings.py
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# Flask stuff:
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instance/
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.webassets-cache
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# Scrapy stuff:
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.scrapy
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# Sphinx documentation
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docs/_build/
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# PyBuilder
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target/
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# IPython Notebook
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.ipynb_checkpoints
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# pyenv
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.python-version
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# celery beat schedule file
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celerybeat-schedule
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# dotenv
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.env
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# virtualenv
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venv/
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ENV/
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# Spyder project settings
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.spyderproject
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# Rope project settings
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.ropeproject
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6
LICENSE
6
LICENSE
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@ -1,6 +1,6 @@
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Unless otherwise noted, LiteDRAM is
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Unless otherwise noted, LiteDRAM is Copyright 2012-2018 / EnjoyDigital
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Copyright 2012-2016 / EnjoyDigital
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Copyright 2007-2016 / M-Labs
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Initial development is based on MiSoC's LASMICON / Copyright 2007-2016 / M-Labs
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Redistribution and use in source and binary forms, with or without modification,
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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are permitted provided that the following conditions are met:
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43
README
43
README
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@ -3,10 +3,10 @@
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/ /__/ / __/ -_) // / , _/ __ |/ /|_/ /
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/ /__/ / __/ -_) // / , _/ __ |/ /|_/ /
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/____/_/\__/\__/____/_/|_/_/ |_/_/ /_/
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/____/_/\__/\__/____/_/|_/_/ |_/_/ /_/
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Copyright 2015-2017 / EnjoyDigital
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Copyright 2015-2018 / EnjoyDigital
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A small footprint and configurable DRAM core
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A small footprint and configurable DRAM core
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powered by LiteX & Migen
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[> Intro
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[> Intro
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--------
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--------
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@ -16,19 +16,16 @@ LiteDRAM is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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complex FPGA cores by providing simple, elegant and efficient implementations
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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configurable.
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LiteDRAM uses technologies developed in partnership with M-Labs Ltd:
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LiteDRAM is built using LiteX and uses technologies developed in partnership with
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M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteDRAM can be used as a Migen/MiSoC library (by simply installing it
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LiteDRAM can be used as LiteX library or can be integrated with your standard
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with the provided setup.py) or can be integrated with your standard design flow
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design flow by generating the verilog rtl that you will use as a standard core.
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by generating the verilog rtl that you will use as a standard core.
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[> Features
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[> Features
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-----------
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-----------
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@ -47,29 +44,42 @@ Frontend:
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- DMA reader/writer.
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- DMA reader/writer.
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- BIST.
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- BIST.
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[> FPGA Proven
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---------------
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LiteDRAM is already used in commercial and open-source designs:
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- HDMI2USB: http://hdmi2usb.tv/home/
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- and others commercial designs...
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[> Possible improvements
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[> Possible improvements
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------------------------
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------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add standardized interfaces (AXI, Avalon-ST)
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- add support for Altera PHYs.
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- add support for Altera PHYs.
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- add support for Lattice PHYs.
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- add support for Lattice PHYs.
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- add more documentation
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- ... See below Support and consulting :)
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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enjoy-digital.fr.
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devel [AT] lists.m-labs.hk.
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[> Getting started
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> Getting started
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------------------
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------------------
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1. Install Python3 and your vendor's software
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1. Install Python3 and your vendor's software
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2. Obtain LiteX and install it:
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2. Obtain LiteX and install it:
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git clone https://github.com/enjoy-digital/litex --recursive
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git clone https://github.com/enjoy-digital/litex --recursive
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cd litex
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cd litex
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python3 setup.py install
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python3 setup.py develop
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cd ..
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cd ..
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3. TODO: add example design(s)
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3. TODO: add/describe example design(s)
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[> Tests
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--------
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Unit tests are available in ./test/.
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To run all the unit tests:
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./setup.py test
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Tests can also be run individually:
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python3 -m unittest test.test_name
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[> License
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[> License
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----------
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----------
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@ -88,8 +98,7 @@ do them if possible:
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-------------------------
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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We love open-source hardware and like sharing our designs with others.
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LiteDRAM is developed and maintained by EnjoyDigital. Initial development
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LiteDRAM is developed and maintained by EnjoyDigital.
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is based on MiSoC's LASMICON.
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If you would like to know more about LiteDRAM or if you are already a happy
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If you would like to know more about LiteDRAM or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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6
setup.py
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setup.py
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from setuptools import find_packages
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from setuptools import find_packages
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if sys.version_info[:3] < (3, 3):
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if sys.version_info[:3] < (3, 5):
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raise SystemExit("You need Python 3.3+")
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raise SystemExit("You need Python 3.5+")
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setup(
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setup(
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name="litedram",
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name="litedram",
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version="0.1",
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version="0.1",
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description="Small footprint and configurable dram core",
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description="Small footprint and configurable DRAM core",
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long_description=open("README").read(),
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long_description=open("README").read(),
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author="Florent Kermarrec",
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author="Florent Kermarrec",
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author_email="florent@enjoy-digital.fr",
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author_email="florent@enjoy-digital.fr",
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