modules: add MT47H64M16

2018-02-06 19:19:14 +01:00 · 2018-02-06 19:19:14 +01:00 · 58389534e6
parent 57c63c1eab
commit 58389534e6
1 changed files with 15 additions and 0 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -143,6 +143,21 @@ class MT47H128M8(SDRAMModule):
    tRFC  = 127.5


+class MT47H64M16(SDRAMModule):
+    memtype = "DDR2"
+    # geometry
+    nbanks = 8
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 15
+    tWTR  = 2
+    tREFI = 7800
+    tRFC  = 127.5
+
+
 class P3R1GE4JGF(SDRAMModule):
    memtype = "DDR2"
    # geometry