uniformize litex cores

.gitignore

@@ -1,5 +1,89 @@
-__pycache__
-*.pyc
-*.egg-info
-*.vcd
-outgoing
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+env/
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+*.egg-info/
+.installed.cfg
+*.egg
+
+# PyInstaller
+#  Usually these files are written by a python script from a template
+#  before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*,cover
+.hypothesis/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+target/
+
+# IPython Notebook
+.ipynb_checkpoints
+
+# pyenv
+.python-version
+
+# celery beat schedule file
+celerybeat-schedule
+
+# dotenv
+.env
+
+# virtualenv
+venv/
+ENV/
+
+# Spyder project settings
+.spyderproject
+
+# Rope project settings
+.ropeproject

LICENSE

@@ -1,6 +1,6 @@
-Unless otherwise noted, LiteDRAM is
-Copyright 2012-2016 / EnjoyDigital
-Copyright 2007-2016 / M-Labs
+Unless otherwise noted, LiteDRAM is Copyright 2012-2018 / EnjoyDigital
+
+Initial development is based on MiSoC's LASMICON / Copyright 2007-2016 / M-Labs
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:

README

@@ -3,10 +3,10 @@
        / /__/ / __/ -_) // / , _/ __ |/ /|_/ /
       /____/_/\__/\__/____/_/|_/_/ |_/_/  /_/
 
-           Copyright 2015-2017 / EnjoyDigital
+           Copyright 2015-2018 / EnjoyDigital
 
        A small footprint and configurable DRAM core
-
+                powered by LiteX & Migen
 
 [> Intro
 --------
@@ -14,21 +14,18 @@ LiteDRAM provides a small footprint and configurable DRAM core.
 
 LiteDRAM is part of LiteX libraries whose aims are to lower entry level of
 complex FPGA cores by providing simple, elegant and efficient implementations
-ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
-
-The core uses simple and specific streaming buses and will provides in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
+of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
 Since Python is used to describe the HDL, the core is highly and easily
 configurable.
 
-LiteDRAM uses technologies developed in partnership with M-Labs Ltd:
+LiteDRAM is built using LiteX and uses technologies developed in partnership with
+M-Labs Ltd:
  - Migen enables generating HDL with Python in an efficient way.
  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
 
-LiteDRAM can be used as a Migen/MiSoC library (by simply installing it
-with the provided setup.py) or can be integrated with your standard design flow
-by generating the verilog rtl that you will use as a standard core.
+LiteDRAM can be used as LiteX library or can be integrated with your standard
+design flow by generating the verilog rtl that you will use as a standard core.
 
 [> Features
 -----------
@@ -47,29 +44,42 @@ Frontend:
   - DMA reader/writer.
   - BIST.
 
+[> FPGA Proven
+---------------
+LiteDRAM is already used in commercial and open-source designs:
+- HDMI2USB: http://hdmi2usb.tv/home/
+- and others commercial designs...
+
 [> Possible improvements
 ------------------------
 - add standardized interfaces (AXI, Avalon-ST)
 - add support for Altera PHYs.
 - add support for Lattice PHYs.
+- add more documentation
 - ... See below Support and consulting :)
 
 If you want to support these features, please contact us at florent [AT]
-enjoy-digital.fr. You can also contact our partner on the public mailing list
-devel [AT] lists.m-labs.hk.
+enjoy-digital.fr.
 
-
-> Getting started
+[> Getting started
 ------------------
 1. Install Python3 and your vendor's software
 
 2. Obtain LiteX and install it:
   git clone https://github.com/enjoy-digital/litex --recursive
   cd litex
-  python3 setup.py install
+  python3 setup.py develop
   cd ..
 
-3. TODO: add example design(s)
+3. TODO: add/describe example design(s)
+
+[> Tests
+--------
+Unit tests are available in ./test/.
+To run all the unit tests:
+  ./setup.py test
+Tests can also be run individually:
+  python3 -m unittest test.test_name
 
 [> License
 ----------
@@ -88,8 +98,7 @@ do them if possible:
 -------------------------
 We love open-source hardware and like sharing our designs with others.
 
-LiteDRAM is developed and maintained by EnjoyDigital. Initial development
-is based on MiSoC's LASMICON.
+LiteDRAM is developed and maintained by EnjoyDigital.
 
 If you would like to know more about LiteDRAM or if you are already a happy
 user and would like to extend it for your needs, EnjoyDigital can provide standard

setup.py

@@ -5,14 +5,14 @@ from setuptools import setup
 from setuptools import find_packages
 
 
-if sys.version_info[:3] < (3, 3):
-    raise SystemExit("You need Python 3.3+")
+if sys.version_info[:3] < (3, 5):
+    raise SystemExit("You need Python 3.5+")
 
 
 setup(
     name="litedram",
     version="0.1",
-    description="Small footprint and configurable dram core",
+    description="Small footprint and configurable DRAM core",
     long_description=open("README").read(),
     author="Florent Kermarrec",
     author_email="florent@enjoy-digital.fr",