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litedram/address_mapping Add bank_byte_alignment

This commit is contained in:
Dolu1990 2024-07-18 17:51:23 +02:00
parent 5ece090155
commit 49688a52ce
2 changed files with 8 additions and 2 deletions
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8
litedram/core/controller.py
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@ -40,7 +40,13 @@ class ControllerSettings(Settings):
with_auto_precharge = True, with_auto_precharge = True,
# Address mapping # Address mapping
address_mapping = "ROW_BANK_COL"): address_mapping = "ROW_BANK_COL",
# bank_byte_alignment specify how many bytes should be in between each bank change (minimum).
# This is usefull when you want to match a L2 cache sets size.
# For instance you have a L2 cache of 256KB with 4 ways => Sets size of 256KB/4=64KB
# => Ideal bank_byte_alignment = 0x10000
bank_byte_alignment = 0):
self.set_attributes(locals()) self.set_attributes(locals())
# Controller --------------------------------------------------------------------------------------- # Controller ---------------------------------------------------------------------------------------

2
litedram/core/crossbar.py
View File

@ -127,7 +127,7 @@ class LiteDRAMCrossbar(Module):
nmasters = len(self.masters) nmasters = len(self.masters)
# Address mapping -------------------------------------------------------------------------- # Address mapping --------------------------------------------------------------------------
cba_shifts = {"ROW_BANK_COL": controller.settings.geom.colbits - controller.address_align} cba_shifts = {"ROW_BANK_COL": max(controller.settings.geom.colbits - controller.address_align, log2_int(controller.settings.bank_byte_alignment //(controller.data_width // 8))) }
cba_shift = cba_shifts[controller.settings.address_mapping] cba_shift = cba_shifts[controller.settings.address_mapping]
m_ba = [m.get_bank_address(self.bank_bits, cba_shift)for m in self.masters] m_ba = [m.get_bank_address(self.bank_bits, cba_shift)for m in self.masters]
m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, cba_shift) for m in self.masters] m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, cba_shift) for m in self.masters]