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phy/s7/usddrphy: set default cmd_latency to 0. 

Now that we are restricting cmd/clk scan in liblitedram, cmd_latency=0 seems
to be workin for all configurations.
This commit is contained in:
Florent Kermarrec 2020-12-08 10:05:09 +01:00
parent af979bbd31
commit 496cd27a3d
2 changed files with 4 additions and 4 deletions
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6
litedram/phy/s7ddrphy.py
View File

@ -29,7 +29,7 @@ class S7DDRPHY(Module, AutoCSR):
nphases = 4, nphases = 4,
sys_clk_freq = 100e6, sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6,
cmd_latency = 1, cmd_latency = 0,
cmd_delay = None): cmd_delay = None):
assert not (memtype == "DDR3" and nphases == 2) assert not (memtype == "DDR3" and nphases == 2)
phytype = self.__class__.__name__ phytype = self.__class__.__name__
@ -461,5 +461,5 @@ class K7DDRPHY(S7DDRPHY):
# Xilinx Artix7 (S7DDRPHY without odelay, sys2/4x_dqs generated in CRG with 90° phase vs sys2/4x) -- # Xilinx Artix7 (S7DDRPHY without odelay, sys2/4x_dqs generated in CRG with 90° phase vs sys2/4x) --
class A7DDRPHY(S7DDRPHY): class A7DDRPHY(S7DDRPHY):
def __init__(self, pads, cmd_latency=0, **kwargs): def __init__(self, pads, **kwargs):
S7DDRPHY.__init__(self, pads, with_odelay=False, cmd_latency=cmd_latency, **kwargs) S7DDRPHY.__init__(self, pads, with_odelay=False, **kwargs)

2
litedram/phy/usddrphy.py
View File

@ -28,7 +28,7 @@ class USDDRPHY(Module, AutoCSR):
memtype = "DDR3", memtype = "DDR3",
sys_clk_freq = 100e6, sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6,
cmd_latency = 1, cmd_latency = 0,
cmd_delay = None, cmd_delay = None,
is_rdimm = False): is_rdimm = False):
phytype = self.__class__.__name__ phytype = self.__class__.__name__