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modules: Add IS43TR16512B.

This commit is contained in:
Florent Kermarrec 2021-09-30 15:44:14 +02:00
parent 3afd617455
commit 4adfff2c8b
1 changed files with 11 additions and 0 deletions
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11
litedram/modules.py
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@ -773,6 +773,17 @@ class IS43TR16256A(DDR3Module):
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
class IS43TR16512B(DDR3Module):
# geometry
nbanks = 8
nrows = 65536
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
speedgrade_timings = {
"1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=35),
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
# DDR3 (SO-DIMM) -----------------------------------------------------------------------------------