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core/refresher: remove req/ack signal and use stream
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parent
3d9ea833dd
commit
4c1b97b465
2 changed files with 12 additions and 10 deletions
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@ -159,7 +159,7 @@ class Multiplexer(Module, AutoCSR):
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write_time_en, max_write_time = anti_starvation(settings.write_time)
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write_time_en, max_write_time = anti_starvation(settings.write_time)
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# Refresh
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# Refresh
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self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
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self.comb += [bm.refresh_req.eq(refresher.cmd.valid) for bm in bank_machines]
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go_to_refresh = Signal()
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go_to_refresh = Signal()
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bm_refresh_gnts = [bm.refresh_gnt for bm in bank_machines]
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bm_refresh_gnts = [bm.refresh_gnt for bm in bank_machines]
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self.comb += go_to_refresh.eq(reduce(and_, bm_refresh_gnts))
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self.comb += go_to_refresh.eq(reduce(and_, bm_refresh_gnts))
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@ -228,8 +228,8 @@ class Multiplexer(Module, AutoCSR):
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)
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)
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fsm.act("REFRESH",
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fsm.act("REFRESH",
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steerer.sel[0].eq(STEER_REFRESH),
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steerer.sel[0].eq(STEER_REFRESH),
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refresher.ack.eq(1),
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refresher.cmd.ready.eq(1),
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If(~refresher.req,
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If(refresher.cmd.valid & refresher.cmd.last,
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NextState("READ")
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NextState("READ")
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)
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)
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)
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)
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@ -1,14 +1,15 @@
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from litex.gen import *
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from litex.gen import *
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from litex.gen.genlib.misc import timeline, WaitTimer
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from litex.gen.genlib.misc import timeline, WaitTimer
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from litex.soc.interconnect import stream
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from litedram.core.multiplexer import *
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from litedram.core.multiplexer import *
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class Refresher(Module):
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class Refresher(Module):
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def __init__(self, settings):
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def __init__(self, settings):
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self.req = Signal()
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# 1st command 1 cycle after assertion of ready
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self.ack = Signal() # 1st command 1 cycle after assertion of ack
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self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(settings.geom.addressbits,
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self.cmd = cmd = Record(cmd_request_layout(settings.geom.addressbits,
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settings.geom.bankbits))
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settings.geom.bankbits))
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# # #
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# # #
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@ -51,15 +52,16 @@ class Refresher(Module):
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)
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)
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)
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)
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fsm.act("WAIT_GRANT",
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fsm.act("WAIT_GRANT",
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self.req.eq(1),
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cmd.valid.eq(1),
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If(self.ack,
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If(cmd.ready,
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seq_start.eq(1),
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seq_start.eq(1),
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NextState("WAIT_SEQ")
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NextState("WAIT_SEQ")
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)
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)
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)
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)
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fsm.act("WAIT_SEQ",
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fsm.act("WAIT_SEQ",
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self.req.eq(1),
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cmd.valid.eq(1),
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If(seq_done,
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If(seq_done,
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cmd.last.eq(1),
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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)
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)
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