core/refresher: remove req/ack signal and use stream

This commit is contained in:
Florent Kermarrec 2016-05-03 17:45:57 +02:00
parent 3d9ea833dd
commit 4c1b97b465
2 changed files with 12 additions and 10 deletions

View file

@ -159,7 +159,7 @@ class Multiplexer(Module, AutoCSR):
write_time_en, max_write_time = anti_starvation(settings.write_time) write_time_en, max_write_time = anti_starvation(settings.write_time)
# Refresh # Refresh
self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines] self.comb += [bm.refresh_req.eq(refresher.cmd.valid) for bm in bank_machines]
go_to_refresh = Signal() go_to_refresh = Signal()
bm_refresh_gnts = [bm.refresh_gnt for bm in bank_machines] bm_refresh_gnts = [bm.refresh_gnt for bm in bank_machines]
self.comb += go_to_refresh.eq(reduce(and_, bm_refresh_gnts)) self.comb += go_to_refresh.eq(reduce(and_, bm_refresh_gnts))
@ -228,8 +228,8 @@ class Multiplexer(Module, AutoCSR):
) )
fsm.act("REFRESH", fsm.act("REFRESH",
steerer.sel[0].eq(STEER_REFRESH), steerer.sel[0].eq(STEER_REFRESH),
refresher.ack.eq(1), refresher.cmd.ready.eq(1),
If(~refresher.req, If(refresher.cmd.valid & refresher.cmd.last,
NextState("READ") NextState("READ")
) )
) )

View file

@ -1,14 +1,15 @@
from litex.gen import * from litex.gen import *
from litex.gen.genlib.misc import timeline, WaitTimer from litex.gen.genlib.misc import timeline, WaitTimer
from litex.soc.interconnect import stream
from litedram.core.multiplexer import * from litedram.core.multiplexer import *
class Refresher(Module): class Refresher(Module):
def __init__(self, settings): def __init__(self, settings):
self.req = Signal() # 1st command 1 cycle after assertion of ready
self.ack = Signal() # 1st command 1 cycle after assertion of ack self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(settings.geom.addressbits,
self.cmd = cmd = Record(cmd_request_layout(settings.geom.addressbits,
settings.geom.bankbits)) settings.geom.bankbits))
# # # # # #
@ -51,15 +52,16 @@ class Refresher(Module):
) )
) )
fsm.act("WAIT_GRANT", fsm.act("WAIT_GRANT",
self.req.eq(1), cmd.valid.eq(1),
If(self.ack, If(cmd.ready,
seq_start.eq(1), seq_start.eq(1),
NextState("WAIT_SEQ") NextState("WAIT_SEQ")
) )
) )
fsm.act("WAIT_SEQ", fsm.act("WAIT_SEQ",
self.req.eq(1), cmd.valid.eq(1),
If(seq_done, If(seq_done,
cmd.last.eq(1),
NextState("IDLE") NextState("IDLE")
) )
) )