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modules: add MT40A512M8 DDR4.

This commit is contained in:
Florent Kermarrec 2020-03-10 13:56:13 +01:00
parent 183f1a6e27
commit 4ec676db27
1 changed files with 20 additions and 1 deletions
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21
litedram/modules.py
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@ -551,7 +551,7 @@ class MT40A256M16(SDRAMModule):
ncols = 1024
# timings
trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
trfc = {"1x": (None, 260), "2x": (None, 160), "4x": (None, 110)}
trfc = {"1x": (None, 260), "2x": (None, 160), "4x": (None, 110)}
technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
speedgrade_timings = {
"2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(28, 35), tRAS=32),
@ -559,6 +559,25 @@ class MT40A256M16(SDRAMModule):
speedgrade_timings["default"] = speedgrade_timings["2400"]
class MT40A512M8(SDRAMModule):
memtype = "DDR4"
# geometry
ngroupbanks = 4
ngroups = 4
nbanks = ngroups * ngroupbanks
nrows = 32768
ncols = 1024
# timings
trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
trfc = {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
speedgrade_timings = {
"2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
"2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=trfc, tFAW=(20, 21), tRAS=32),
}
speedgrade_timings["default"] = speedgrade_timings["2400"]
class MT40A512M16(SDRAMModule):
memtype = "DDR4"
# geometry