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litedram
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Fix generation with no CPU 

The various UART bits in there need to be skipped

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2021-09-22 21:01:56 +10:00
parent 053434b9df
commit 4fdb9a2cf2
1 changed files with 28 additions and 26 deletions
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54
litedram/gen.py
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@ -466,11 +466,6 @@ class LiteDRAMCoreControl(Module, AutoCSR):
class LiteDRAMCore(SoCCore): class LiteDRAMCore(SoCCore):
def __init__(self, platform, core_config, **kwargs): def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
if core_config["uart"] == "fifo":
platform.add_extension(get_uart_fifo_ios())
else:
platform.add_extension(get_uart_std_ios())
# Parameters ------------------------------------------------------------------------------- # Parameters -------------------------------------------------------------------------------
sys_clk_freq = core_config["sys_clk_freq"] sys_clk_freq = core_config["sys_clk_freq"]
@ -485,39 +480,46 @@ class LiteDRAMCore(SoCCore):
kwargs["with_timer"] = False kwargs["with_timer"] = False
kwargs["with_ctrl"] = False kwargs["with_ctrl"] = False
platform.add_extension(get_common_ios())
if cpu_type is not None:
if core_config["uart"] == "fifo":
platform.add_extension(get_uart_fifo_ios())
else:
platform.add_extension(get_uart_std_ios())
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type = cpu_type, cpu_type = cpu_type,
cpu_variant = cpu_variant, cpu_variant = cpu_variant,
csr_data_width = csr_data_width, csr_data_width = csr_data_width,
with_uart = False,
**kwargs) **kwargs)
# UART ------------------------------------------------------------------------------------- # UART -------------------------------------------------------------------------------------
assert uart_type in ["rs232", "fifo"] if cpu_type is not None:
if uart_type == "fifo": assert uart_type in ["rs232", "fifo"]
uart_interface = RS232PHYInterface() if uart_type == "fifo":
self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1) uart_interface = RS232PHYInterface()
uart_tx_pads = platform.request("uart_tx") self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1)
uart_rx_pads = platform.request("uart_rx") uart_tx_pads = platform.request("uart_tx")
self.comb += [ uart_rx_pads = platform.request("uart_rx")
# UART TX. self.comb += [
# UART TX.
uart_tx_pads.valid.eq(uart_interface.sink.valid), uart_tx_pads.valid.eq(uart_interface.sink.valid),
uart_interface.sink.ready.eq(uart_tx_pads.ready), uart_interface.sink.ready.eq(uart_tx_pads.ready),
uart_tx_pads.data.eq(uart_interface.sink.data), uart_tx_pads.data.eq(uart_interface.sink.data),
# UART RX. # UART RX.
uart_interface.source.valid.eq(uart_rx_pads.valid), uart_interface.source.valid.eq(uart_rx_pads.valid),
uart_rx_pads.ready.eq(uart_interface.source.ready), uart_rx_pads.ready.eq(uart_interface.source.ready),
uart_interface.source.data.eq(uart_rx_pads.data) uart_interface.source.data.eq(uart_rx_pads.data)
] ]
else: else:
self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200) self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200)
self.submodules.uart = UART(self.uart_phy) self.submodules.uart = UART(self.uart_phy)
if self.irq.enabled: if self.irq.enabled:
self.irq.add("uart", use_loc_if_exists=True) self.irq.add("uart", use_loc_if_exists=True)
else: else:
self.add_constant("UART_POLLING") self.add_constant("UART_POLLING")
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
if isinstance(platform, SimPlatform): if isinstance(platform, SimPlatform):