Fix generation with no CPU

The various UART bits in there need to be skipped

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2021-09-22 21:01:56 +10:00
parent 053434b9df
commit 4fdb9a2cf2
1 changed files with 28 additions and 26 deletions

View File

@ -466,11 +466,6 @@ class LiteDRAMCoreControl(Module, AutoCSR):
class LiteDRAMCore(SoCCore):
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
if core_config["uart"] == "fifo":
platform.add_extension(get_uart_fifo_ios())
else:
platform.add_extension(get_uart_std_ios())
# Parameters -------------------------------------------------------------------------------
sys_clk_freq = core_config["sys_clk_freq"]
@ -485,15 +480,22 @@ class LiteDRAMCore(SoCCore):
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
platform.add_extension(get_common_ios())
if cpu_type is not None:
if core_config["uart"] == "fifo":
platform.add_extension(get_uart_fifo_ios())
else:
platform.add_extension(get_uart_std_ios())
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type = cpu_type,
cpu_variant = cpu_variant,
csr_data_width = csr_data_width,
with_uart = False,
**kwargs)
# UART -------------------------------------------------------------------------------------
if cpu_type is not None:
assert uart_type in ["rs232", "fifo"]
if uart_type == "fifo":
uart_interface = RS232PHYInterface()