Fix generation with no CPU
The various UART bits in there need to be skipped Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -466,11 +466,6 @@ class LiteDRAMCoreControl(Module, AutoCSR):
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class LiteDRAMCore(SoCCore):
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def __init__(self, platform, core_config, **kwargs):
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platform.add_extension(get_common_ios())
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if core_config["uart"] == "fifo":
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platform.add_extension(get_uart_fifo_ios())
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else:
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platform.add_extension(get_uart_std_ios())
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# Parameters -------------------------------------------------------------------------------
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sys_clk_freq = core_config["sys_clk_freq"]
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@ -485,15 +480,22 @@ class LiteDRAMCore(SoCCore):
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kwargs["with_timer"] = False
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kwargs["with_ctrl"] = False
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platform.add_extension(get_common_ios())
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if cpu_type is not None:
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if core_config["uart"] == "fifo":
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platform.add_extension(get_uart_fifo_ios())
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else:
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platform.add_extension(get_uart_std_ios())
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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cpu_type = cpu_type,
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cpu_variant = cpu_variant,
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csr_data_width = csr_data_width,
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with_uart = False,
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**kwargs)
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# UART -------------------------------------------------------------------------------------
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if cpu_type is not None:
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assert uart_type in ["rs232", "fifo"]
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if uart_type == "fifo":
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uart_interface = RS232PHYInterface()
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