PhySettings: add databits to allow SoC to compute memory size more easily

litedram/common.py

@@ -21,7 +21,7 @@ class Settings:
 
 
 class PhySettings(Settings):
-    def __init__(self, memtype, dfi_databits,
+    def __init__(self, memtype, databits, dfi_databits,
                  nphases,
                  rdphase, wrphase,
                  rdcmdphase, wrcmdphase,

litedram/phy/ecp5ddrphy.py

@@ -138,6 +138,7 @@ class ECP5DDRPHY(Module, AutoCSR):
         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
         self.settings = PhySettings(
             memtype=memtype,
+            databits=databits,
             dfi_databits=4*databits,
             nranks=nranks,
             nphases=nphases,

litedram/phy/gensdrphy.py

@@ -31,6 +31,7 @@ class GENSDRPHY(Module):
 
         self.settings = PhySettings(
             memtype="SDR",
+            databits=databits,
             dfi_databits=databits,
             nranks=nranks,
             nphases=1,

litedram/phy/s6ddrphy.py

@@ -43,6 +43,7 @@ class S6HalfRateDDRPHY(Module):
         if memtype == "DDR3":
             self.settings = PhySettings(
                 memtype="DDR3",
+                databits=databits,
                 dfi_databits=2*databits,
                 nranks=nranks,
                 nphases=nphases,
@@ -58,6 +59,7 @@ class S6HalfRateDDRPHY(Module):
         else:
             self.settings = PhySettings(
                 memtype=memtype,
+                databits=databits,
                 dfi_databits=2*databits,
                 nranks=nranks,
                 nphases=nphases,

litedram/phy/s7ddrphy.py

@@ -94,6 +94,7 @@ class S7DDRPHY(Module, AutoCSR):
         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
         self.settings = PhySettings(
             memtype=memtype,
+            databits=databits,
             dfi_databits=2*databits,
             nranks=nranks,
             nphases=nphases,

litedram/phy/usddrphy.py

@@ -106,6 +106,7 @@ class USDDRPHY(Module, AutoCSR):
         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
         self.settings = PhySettings(
             memtype=memtype,
+            databits=databits,
             dfi_databits=2*databits,
             nranks=nranks,
             nphases=nphases,