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https://github.com/enjoy-digital/litedram.git
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phy/usddrphy: move DDR4DFIMux to dfi.py
This commit is contained in:
Florent Kermarrec
parent
f861d99903
commit
59c1289432
2 changed files with 53 additions and 56 deletions
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@ -75,3 +75,21 @@ class Interface(Record):
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class Interconnect(Module):
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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class DDR4DFIMux(Module):
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def __init__(self, dfi_i, dfi_o):
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for i in range(len(dfi_i.phases)):
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p_i = dfi_i.phases[i]
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p_o = dfi_o.phases[i]
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self.comb += [
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p_i.connect(p_o),
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If(~p_i.ras_n & p_i.cas_n & p_i.we_n,
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p_o.act_n.eq(0),
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p_o.we_n.eq(p_i.address[14]),
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p_o.cas_n.eq(p_i.address[15]),
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p_o.ras_n.eq(p_i.address[16])
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).Else(
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p_o.act_n.eq(1),
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)
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]
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@ -16,24 +16,6 @@ from litedram.common import *
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from litedram.phy.dfi import *
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class DDR4DFIMux(Module):
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def __init__(self, dfi_i, dfi_o):
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for i in range(len(dfi_i.phases)):
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p_i = dfi_i.phases[i]
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p_o = dfi_o.phases[i]
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self.comb += [
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p_i.connect(p_o),
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If(~p_i.ras_n & p_i.cas_n & p_i.we_n,
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p_o.act_n.eq(0),
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p_o.we_n.eq(p_i.address[14]),
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p_o.cas_n.eq(p_i.address[15]),
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p_o.ras_n.eq(p_i.address[16])
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).Else(
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p_o.act_n.eq(1),
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)
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]
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class USDDRPHY(Module, AutoCSR):
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def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6, iodelay_clk_freq=200e6, cmd_latency=0):
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tck = 2/(2*4*sys_clk_freq)
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@ -94,13 +76,10 @@ class USDDRPHY(Module, AutoCSR):
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write_latency=cwl_sys_latency
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)
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self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
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if memtype == "DDR3":
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_dfi = self.dfi
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else:
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_dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
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dfi_mux = DDR4DFIMux(self.dfi, _dfi)
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self.submodules += dfi_mux
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self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
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if memtype == "DDR4":
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dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
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self.submodules += DDR4DFIMux(self.dfi, dfi)
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# # #
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@ -146,10 +125,10 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ=a_o_nodelay,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D=Cat(_dfi.phases[0].address[i], _dfi.phases[0].address[i],
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_dfi.phases[1].address[i], _dfi.phases[1].address[i],
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_dfi.phases[2].address[i], _dfi.phases[2].address[i],
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_dfi.phases[3].address[i], _dfi.phases[3].address[i])
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i_D=Cat(dfi.phases[0].address[i], dfi.phases[0].address[i],
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dfi.phases[1].address[i], dfi.phases[1].address[i],
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dfi.phases[2].address[i], dfi.phases[2].address[i],
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dfi.phases[3].address[i], dfi.phases[3].address[i])
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),
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Instance("ODELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
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@ -180,10 +159,10 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ=ba_o_nodelay,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D=Cat(_dfi.phases[0].bank[i], _dfi.phases[0].bank[i],
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_dfi.phases[1].bank[i], _dfi.phases[1].bank[i],
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_dfi.phases[2].bank[i], _dfi.phases[2].bank[i],
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_dfi.phases[3].bank[i], _dfi.phases[3].bank[i])
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i_D=Cat(dfi.phases[0].bank[i], dfi.phases[0].bank[i],
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dfi.phases[1].bank[i], dfi.phases[1].bank[i],
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dfi.phases[2].bank[i], dfi.phases[2].bank[i],
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dfi.phases[3].bank[i], dfi.phases[3].bank[i])
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),
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Instance("ODELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
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@ -215,10 +194,10 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ=x_o_nodelay,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D=Cat(getattr(_dfi.phases[0], name), getattr(_dfi.phases[0], name),
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getattr(_dfi.phases[1], name), getattr(_dfi.phases[1], name),
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getattr(_dfi.phases[2], name), getattr(_dfi.phases[2], name),
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getattr(_dfi.phases[3], name), getattr(_dfi.phases[3], name))
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i_D=Cat(getattr(dfi.phases[0], name), getattr(dfi.phases[0], name),
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getattr(dfi.phases[1], name), getattr(dfi.phases[1], name),
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getattr(dfi.phases[2], name), getattr(dfi.phases[2], name),
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getattr(dfi.phases[3], name), getattr(dfi.phases[3], name))
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),
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Instance("ODELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
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@ -256,10 +235,10 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ=dm_o_nodelay,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D=Cat(_dfi.phases[0].wrdata_mask[i], _dfi.phases[0].wrdata_mask[databits//8+i],
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_dfi.phases[1].wrdata_mask[i], _dfi.phases[1].wrdata_mask[databits//8+i],
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_dfi.phases[2].wrdata_mask[i], _dfi.phases[2].wrdata_mask[databits//8+i],
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_dfi.phases[3].wrdata_mask[i], _dfi.phases[3].wrdata_mask[databits//8+i])
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i_D=Cat(dfi.phases[0].wrdata_mask[i], dfi.phases[0].wrdata_mask[databits//8+i],
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dfi.phases[1].wrdata_mask[i], dfi.phases[1].wrdata_mask[databits//8+i],
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dfi.phases[2].wrdata_mask[i], dfi.phases[2].wrdata_mask[databits//8+i],
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dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i])
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)
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self.specials += \
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Instance("ODELAYE3",
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@ -350,10 +329,10 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ=dq_o_nodelay, o_T_OUT=dq_t,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D=Cat(_dfi.phases[0].wrdata[i], _dfi.phases[0].wrdata[databits+i],
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_dfi.phases[1].wrdata[i], _dfi.phases[1].wrdata[databits+i],
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_dfi.phases[2].wrdata[i], _dfi.phases[2].wrdata[databits+i],
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_dfi.phases[3].wrdata[i], _dfi.phases[3].wrdata[databits+i]),
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i_D=Cat(dfi.phases[0].wrdata[i], dfi.phases[0].wrdata[databits+i],
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dfi.phases[1].wrdata[i], dfi.phases[1].wrdata[databits+i],
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dfi.phases[2].wrdata[i], dfi.phases[2].wrdata[databits+i],
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dfi.phases[3].wrdata[i], dfi.phases[3].wrdata[databits+i]),
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i_T=~oe_dq
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),
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Instance("ISERDESE3",
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@ -400,15 +379,15 @@ class USDDRPHY(Module, AutoCSR):
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)
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]
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self.comb += [
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_dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]),
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_dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]),
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_dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]),
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_dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]),
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dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]),
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dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]),
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dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]),
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dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]),
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_dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
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_dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
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_dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
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_dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]),
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dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
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dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
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dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
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dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]),
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]
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# Flow control
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@ -418,19 +397,19 @@ class USDDRPHY(Module, AutoCSR):
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# cl_sys_latency cycles CAS
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# 2 cycles through ISERDESE2
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# 3 cycles through Bitslip
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rddata_en = _dfi.phases[self.settings.rdphase].rddata_en
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rddata_en = dfi.phases[self.settings.rdphase].rddata_en
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for i in range(self.settings.read_latency-1):
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n_rddata_en = Signal()
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self.sync += n_rddata_en.eq(rddata_en)
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rddata_en = n_rddata_en
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for phase in _dfi.phases:
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for phase in dfi.phases:
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phase_rddata_valid = Signal()
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self.sync += phase_rddata_valid.eq(rddata_en | self._wlevel_en.storage)
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self.comb += phase.rddata_valid.eq(phase_rddata_valid)
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oe = Signal()
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last_wrdata_en = Signal(cwl_sys_latency+2)
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wrphase = _dfi.phases[self.settings.wrphase]
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wrphase = dfi.phases[self.settings.wrphase]
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self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1]))
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self.comb += oe.eq(
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last_wrdata_en[cwl_sys_latency-1] |
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