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bench/arty/kc705: Use PHYPadsReducer to easily test various DFI sizes.

This commit is contained in:
Florent Kermarrec 2021-07-09 17:58:33 +02:00
parent 894c7fb49e
commit 5a4ed3d204
2 changed files with 6 additions and 2 deletions
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4
bench/arty.py
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@ -18,6 +18,7 @@ from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.common import PHYPadsReducer
from litedram.phy import s7ddrphy from litedram.phy import s7ddrphy
from litedram.modules import MT41K128M16 from litedram.modules import MT41K128M16
@ -82,7 +83,8 @@ class BenchSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)

4
bench/kc705.py
View File

@ -18,6 +18,7 @@ from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.common import PHYPadsReducer
from litedram.phy import s7ddrphy from litedram.phy import s7ddrphy
from litedram.modules import MT8JTF12864 from litedram.modules import MT8JTF12864
@ -75,7 +76,8 @@ class BenchSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)