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gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz.

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Jean-François Nguyen 2021-08-03 16:41:45 +02:00 committed by Florent Kermarrec
parent 2b0f806c96
commit 5aad6cd3d1
1 changed files with 2 additions and 3 deletions
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5
litedram/gen.py
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@ -557,15 +557,14 @@ class LiteDRAMCore(SoCCore):
# Sim.
if isinstance(platform, SimPlatform):
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = core_config["sdram_module_nb"]*8,
clk_freq = sdram_clk_freq)
clk_freq = sys_clk_freq)
self.submodules.ddrphy = sdram_phy = SDRAMPHYModel(
module = sdram_module,
settings = phy_settings,
clk_freq = sdram_clk_freq)
clk_freq = sys_clk_freq)
# GENSDRPHY.
elif core_config["sdram_phy"] in [litedram_phys.GENSDRPHY]: